diff options
| author | Philipp Zabel <p.zabel@pengutronix.de> | 2012-07-02 09:03:55 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-09-26 16:29:37 -0300 |
| commit | 1043667b1763feac06654c9bf7263b215df2c893 (patch) | |
| tree | 6a23e1ce991d4a5953952bcf19d2c176446575a2 /drivers/media/platform/coda.h | |
| parent | df1e74cc04dbc0d2fada237333b91e167b09dd30 (diff) | |
[media] media: coda: fix IRAM/AXI handling for i.MX53
This uses the ARCH_MXC specific iram_alloc API to allocate a work
buffer in the SoC's on-chip SRAM and sets up the AXI_SRAM_USE
register. In the future, the allocation will be converted to use
the genalloc API.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Javier Martin <javier.martin@vista-silicon.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/platform/coda.h')
| -rw-r--r-- | drivers/media/platform/coda.h | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/drivers/media/platform/coda.h b/drivers/media/platform/coda.h index 3fbb315c8fbe..332401033194 100644 --- a/drivers/media/platform/coda.h +++ b/drivers/media/platform/coda.h @@ -45,7 +45,12 @@ #define CODA_IMAGE_ENDIAN_SELECT (1 << 0) #define CODA_REG_BIT_RD_PTR(x) (0x120 + 8 * (x)) #define CODA_REG_BIT_WR_PTR(x) (0x124 + 8 * (x)) -#define CODA_REG_BIT_SEARCH_RAM_BASE_ADDR 0x140 +#define CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR 0x140 +#define CODA7_REG_BIT_AXI_SRAM_USE 0x140 +#define CODA7_USE_BIT_ENABLE (1 << 0) +#define CODA7_USE_HOST_BIT_ENABLE (1 << 7) +#define CODA7_USE_ME_ENABLE (1 << 4) +#define CODA7_USE_HOST_ME_ENABLE (1 << 11) #define CODA_REG_BIT_BUSY 0x160 #define CODA_REG_BIT_BUSY_FLAG 1 #define CODA_REG_BIT_RUN_COMMAND 0x164 @@ -162,11 +167,13 @@ #define CODA_RATECONTROL_ENABLE_MASK 0x01 #define CODA_CMD_ENC_SEQ_RC_BUF_SIZE 0x1b0 #define CODA_CMD_ENC_SEQ_INTRA_REFRESH 0x1b4 -#define CODA_CMD_ENC_SEQ_FMO 0x1b8 +#define CODADX6_CMD_ENC_SEQ_FMO 0x1b8 #define CODA_FMOPARAM_TYPE_OFFSET 4 #define CODA_FMOPARAM_TYPE_MASK 1 #define CODA_FMOPARAM_SLICENUM_OFFSET 0 #define CODA_FMOPARAM_SLICENUM_MASK 0x0f +#define CODA7_CMD_ENC_SEQ_SEARCH_BASE 0x1b8 +#define CODA7_CMD_ENC_SEQ_SEARCH_SIZE 0x1bc #define CODA_CMD_ENC_SEQ_RC_QP_MAX 0x1c8 #define CODA_QPMAX_OFFSET 0 #define CODA_QPMAX_MASK 0x3f @@ -189,8 +196,14 @@ #define CODA_RET_ENC_PIC_FLAG 0x1d0 /* Set Frame Buffer */ -#define CODA_CMD_SET_FRAME_BUF_NUM 0x180 -#define CODA_CMD_SET_FRAME_BUF_STRIDE 0x184 +#define CODA_CMD_SET_FRAME_BUF_NUM 0x180 +#define CODA_CMD_SET_FRAME_BUF_STRIDE 0x184 +#define CODA7_CMD_SET_FRAME_AXI_BIT_ADDR 0x190 +#define CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR 0x194 +#define CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR 0x198 +#define CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR 0x19c +#define CODA7_CMD_SET_FRAME_AXI_OVL_ADDR 0x1a0 +#define CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE 0x1a8 /* Encoder Header */ #define CODA_CMD_ENC_HEADER_CODE 0x180 |