diff options
| author | Sri Krishna chowdary <schowdary@nvidia.com> | 2013-11-20 11:02:16 +0530 |
|---|---|---|
| committer | Krishna Reddy <vdumpa@nvidia.com> | 2014-01-29 11:11:00 -0800 |
| commit | 40cf417eeb1fc7c807f88bb6cf75bbab9a2e4dc4 (patch) | |
| tree | b07b88e1d6364f3d7cd7d1b565af35c8cc6cd46a /drivers/iommu | |
| parent | 354b811602129beb6e5cb649549612bd80102e8f (diff) | |
iommu/tegra: smmu: t114: Use PPCS1 for SDMMC
Since AHB_MASTER_SWID_0 does not need a secure write
and also since this is only for T114,
Hardcode this in the driver itself.
Bug 1380855
Change-Id: I336c11d83949b8fe5e578db7e0302a21dde1a186
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/333259
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/tegra-smmu.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index b70f345ca029..0e103761ec55 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -1,7 +1,7 @@ /* * IOMMU driver for SMMU on Tegra 3 series SoCs and later. * - * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -141,6 +141,9 @@ enum { #define AHB_XBAR_CTRL 0xe0 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE 1 #define AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT 17 +#define AHB_MASTER_SWID_0 0x18 +#define AHB_MASTER_SELECT_SDMMC (BIT(9) | BIT(12) \ + | BIT(19) | BIT(20)) #define SMMU_NUM_ASIDS 4 #define SMMU_NUM_ASIDS_TEGRA12 128 @@ -535,6 +538,9 @@ static void smmu_setup_regs(struct smmu_device *smmu) AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT; ahb_write(smmu, val, AHB_XBAR_CTRL); } + /* On T114, Set PPCS1 ASID for SDMMC */ + if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11) + ahb_write(smmu, AHB_MASTER_SELECT_SDMMC, AHB_MASTER_SWID_0); } |