diff options
| author | venkatajagadish <vjagadish@nvidia.com> | 2014-03-14 12:04:03 +0530 |
|---|---|---|
| committer | Laxman Dewangan <ldewangan@nvidia.com> | 2014-03-20 01:05:27 -0700 |
| commit | 7ebdd3d7ef56c8f412ef6d0404f814ae2d4eb67a (patch) | |
| tree | dd76988b64a73c8bd1a3da23bd80f3a67f0f0472 /drivers/ata | |
| parent | 12c2947deb045cc51b6d8f041d5e0b1602fd2b0e (diff) | |
SATA: tegra: Fix SATA write sync issue
It is required to read back the register to make sure
the write operation is completed
Change-Id: I0d9c83451819c3e059256c0f54193290b40ec923
Signed-off-by: venkatajagadish <vjagadish@nvidia.com>
Reviewed-on: http://git-master/r/381906
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat (limited to 'drivers/ata')
| -rw-r--r-- | drivers/ata/ahci-tegra.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/ata/ahci-tegra.c b/drivers/ata/ahci-tegra.c index d894da56008f..dbc7524150b3 100644 --- a/drivers/ata/ahci-tegra.c +++ b/drivers/ata/ahci-tegra.c @@ -480,6 +480,7 @@ static inline void port_writel(u32 val, u32 offset) { AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", PORT_BASE + offset, val); writel(val, IO_ADDRESS(PORT_BASE + offset)); + readl(IO_ADDRESS(PORT_BASE + offset)); } static inline u32 bar5_readl(u32 offset) @@ -496,6 +497,7 @@ static inline void bar5_writel(u32 val, u32 offset) AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_SATA_BAR5_BASE+offset, val); writel(val, IO_ADDRESS(TEGRA_SATA_BAR5_BASE + offset)); + readl(IO_ADDRESS(TEGRA_SATA_BAR5_BASE + offset)); } @@ -513,6 +515,7 @@ static inline void xusb_writel(u32 val, u32 offset) AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_XUSB_PADCTL_BASE+offset, val); writel(val, IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE + offset)); + readl(IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE + offset)); } @@ -528,6 +531,7 @@ static inline void pmc_writel(u32 val, u32 offset) { AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_PMC_BASE+offset, val); writel(val, IO_ADDRESS(TEGRA_PMC_BASE + offset)); + readl(IO_ADDRESS(TEGRA_PMC_BASE + offset)); } static inline u32 clk_readl(u32 offset) @@ -543,6 +547,7 @@ static inline void clk_writel(u32 val, u32 offset) { AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_CLK_RESET_BASE+offset, val); writel(val, IO_ADDRESS(TEGRA_CLK_RESET_BASE + offset)); + readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + offset)); } static inline u32 misc_readl(u32 offset) @@ -558,6 +563,7 @@ static inline void misc_writel(u32 val, u32 offset) { AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_APB_MISC_BASE+offset, val); writel(val, IO_ADDRESS(TEGRA_APB_MISC_BASE + offset)); + readl(IO_ADDRESS(TEGRA_APB_MISC_BASE + offset)); } static inline u32 sata_readl(u32 offset) @@ -573,6 +579,7 @@ static inline void sata_writel(u32 val, u32 offset) { AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_SATA_BASE+offset, val); writel(val, IO_ADDRESS(TEGRA_SATA_BASE + offset)); + readl(IO_ADDRESS(TEGRA_SATA_BASE + offset)); } static inline u32 scfg_readl(u32 offset) @@ -590,6 +597,7 @@ static inline void scfg_writel(u32 val, u32 offset) AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_SATA_CONFIG_BASE+offset, val); writel(val, IO_ADDRESS(TEGRA_SATA_CONFIG_BASE + offset)); + readl(IO_ADDRESS(TEGRA_SATA_CONFIG_BASE + offset)); } static inline u32 pictlr_readl(u32 offset) @@ -607,6 +615,7 @@ static inline void pictlr_writel(u32 val, u32 offset) AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_PRIMARY_ICTLR_BASE+offset, val); writel(val, IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE + offset)); + readl(IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE + offset)); } static inline u32 fuse_readl(u32 offset) |