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| author | Otavio Salvador <otavio@ossystems.com.br> | 2019-03-28 10:47:24 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-28 10:47:24 -0300 |
| commit | 0a8ab17689e628c84a666195bfc6ab85d11cf057 (patch) | |
| tree | 01630dc4a6935df99bf7d11d34ff8d384fed86e2 /arch/x86/include/asm/cpufeatures.h | |
| parent | 1e71d8c630cbc0d1f5d762fd019690b5cdb880ae (diff) | |
| parent | 32aca03c2ce868d3412da0bb6ce6798c7bea357e (diff) | |
Merge pull request #46 from toradex/4.9-2.3.x-imx
4.9 2.3.x imx
Diffstat (limited to 'arch/x86/include/asm/cpufeatures.h')
| -rw-r--r-- | arch/x86/include/asm/cpufeatures.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index c56c24347f15..98444b77fbe3 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -314,6 +314,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ +#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */ #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ |