diff options
| author | Peng Du <pdu@nvidia.com> | 2014-05-20 15:19:26 -0700 |
|---|---|---|
| committer | Mandar Padmawar <mpadmawar@nvidia.com> | 2014-05-30 03:31:04 -0700 |
| commit | 136101a8e3205b2063177baa317a811d5107a717 (patch) | |
| tree | 3c262a6c363dd529a699c6eaa45a6a67c757e993 /arch/arm64 | |
| parent | cd18d2777e10677cdb452b2b34158dd2338b9e80 (diff) | |
arm64: tegra132: fix CPU reset handler
* fix flowctrl programming and apply for both cores
* go through cpu_resume to restore states for core1
Bug 1509408
Bug 1481103
Bug 1518263
Change-Id: Ie28ee2d2a081fdca8eef15c478c8a55644b4d846
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/412272
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/mach-tegra/reset-handler.S | 15 |
1 files changed, 4 insertions, 11 deletions
diff --git a/arch/arm64/mach-tegra/reset-handler.S b/arch/arm64/mach-tegra/reset-handler.S index 03375a57d4f4..46309b792091 100644 --- a/arch/arm64/mach-tegra/reset-handler.S +++ b/arch/arm64/mach-tegra/reset-handler.S @@ -111,26 +111,19 @@ start_ns: mrs x0, mpidr_el1 and x0, x0, #15 -#ifdef CONFIG_SMP - /* Secondary cores */ - cbnz x0, secondary_holding_pen -#endif - - /* Below is only carried out on core0 */ - /* Clear the flow controller flags for this CPU. */ cpu_to_csr_reg x1, x0 ldr x2, =TEGRA_FLOW_CTRL_BASE - ldr x1, [x2, x1] + ldr x3, [x2, x1] /* Clear event & intr flag */ - orr x1, x1, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG + orr x3, x3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG /* enable, cluster_switch, immed, & bitmaps */ mov x0, #0x3ffd - bic x1, x1, x0 - str x1, [x2] + bic x3, x3, x0 + str x3, [x2, x1] done: b cpu_resume |