diff options
| author | Nitin Sehgal <nsehgal@nvidia.com> | 2014-02-03 18:53:57 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2014-02-09 21:54:39 -0800 |
| commit | 0802375a7853070ef45339703ad4bd9f5dfe091d (patch) | |
| tree | 9e51139f4ad2699cb0528069d3edb13965081100 /arch/arm/mm | |
| parent | 7f93a0dddf39f372c064f772f9af6903e91aaacf (diff) | |
arch: arm: mm: dynamic check for secure/non-secure mode.
- Replace compile time flag with runtime selection.
- Same kernel should work in secure and non secure mode
bug 1411345
Change-Id: I7b20121623aa432eaefe00f47115908595590f16
Signed-off-by: Nitin Sehgal <nsehgal@nvidia.com>
Reviewed-on: http://git-master/r/362897
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index fd0aace10a38..e73f85323a11 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -2,6 +2,7 @@ * linux/arch/arm/mm/proc-v7.S * * Copyright (C) 2001 Deep Blue Solutions Ltd. + * Copyright (c) 2001-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -264,9 +265,9 @@ ENTRY(cpu_v7_do_resume) ldmia r0!, {r4 - r6} mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID -#ifndef CONFIG_TEGRA_USE_SECURE_KERNEL - mcr p15, 0, r6, c15, c0, 1 @ diag -#endif + mrc p14, 0, r7, c0, c1, 0 @ dbgdscr + tst r7, #(1 << 18) @ dbgdscr.ns + mcreq p15, 0, r6, c15, c0, 1 @ diag only in secure-mode ldmia r0!, {r7 - r11} mcr p15, 0, r7, c9, c14, 2 @ PMINTENCLR @@ -609,7 +610,11 @@ __v7_setup: 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number teq r0, r10 bne 3f -#ifndef CONFIG_TEGRA_USE_SECURE_KERNEL + str r0, [r12] @ local stack + mrc p14, 0, r0, c0, c1, 0 @ dbgdscr + tst r0, #(1 << 18) @ dbgdscr.ns + ldr r0, [r12] @ restore r0 + bne 3f @ skip in non-secure mode cmp r6, #0x10 @ power ctrl reg added r1p0 mrcge p15, 0, r10, c15, c0, 0 @ read power control register orrge r10, r10, #1 @ enable dynamic clock gating @@ -668,7 +673,6 @@ __v7_setup: orrle r10, r10, #1 << 21 @ set bit #21 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif -#endif 3: mov r10, #0 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |