i2c: tegra: Avoid duplicate write into Tx Fifo

Dvc I2C_DONE_INTR_EN interrupt bit is always enable into dvc
control register3.During normal transaction on dvc i2c bus
sometimes one transaction written two times in TX fifo buffer
because of triggered dvc interrupt.This is causing to corrupt
the next transaction header and send wrong address over dvc
i2c bus.To solve this issue dvc i2c interrupt has to disable
during filling of Tx fifo and enable after that.

Writing last packet into Tx Fifo is generating i2c interrupt
immediately if IE bit is enable in Packet header. Data shared
between isr and normal thread are not in sync. So alway update
these data before writing into Tx fifo.

Updated the following things in code:
(1) Add the code to mask/unmask I2C_DONE_INTR_EN into dvc control reg3
(2) Always updates the i2c driver required field structure data before
writing into Tx Fifo register.
(3) Add the code to handle tx fifo overflow condition also.
(4) Put delay before resetting the controller

BUG 839528

Change-Id: I7780411b474a20f985e1f7993e5ccccbab619bbc
Reviewed-on: http://git-master/r/39985
Reviewed-by: Alok Chauhan <alokc@nvidia.com>
Tested-by: Alok Chauhan <alokc@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

0 files changed, 0 insertions, 0 deletions