diff options
| author | Eric Nelson <eric.nelson@boundarydevices.com> | 2015-01-30 14:07:55 -0700 |
|---|---|---|
| committer | Zefan Li <lizefan@huawei.com> | 2015-04-14 17:34:00 +0800 |
| commit | 708ef3375975121fbe187397f478e17877c67168 (patch) | |
| tree | 8296acb2984784cfa6a8ef94598bae72de45b69a | |
| parent | 6b4a9a084334717868e054002ad7863a3b4cceef (diff) | |
ASoC: sgtl5000: add delay before first I2C access
commit 58cc9c9a175885bbf6bae3acf18233d0a8229a84 upstream.
To quote from section 1.3.1 of the data sheet:
The SGTL5000 has an internal reset that is deasserted
8 SYS_MCLK cycles after all power rails have been brought
up. After this time, communication can start
...
1.0us represents 8 SYS_MCLK cycles at the minimum 8.0 MHz SYS_MCLK.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Zefan Li <lizefan@huawei.com>
| -rw-r--r-- | sound/soc/codecs/sgtl5000.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c index c40b7ca7a143..87cbf14bbdcd 100644 --- a/sound/soc/codecs/sgtl5000.c +++ b/sound/soc/codecs/sgtl5000.c @@ -1238,6 +1238,9 @@ static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) /* wait for all power rails bring up */ udelay(10); + /* Need 8 clocks before I2C accesses */ + udelay(1); + /* read chip information */ reg = snd_soc_read(codec, SGTL5000_CHIP_ID); if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != |