diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2014-05-16 16:07:09 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-07-09 11:21:31 -0700 |
| commit | ae747fdbc8d9828c0279b74052af88b01941e5d3 (patch) | |
| tree | 376ffd830410535bd4475506e485456d82470fbd | |
| parent | 3ebbc9d1feb22dc4c2999f2f5732e6f619a6c8d3 (diff) | |
clk: qcom: Fix mmcc-8974's PLL configurations
commit 437ae6a1b8f2eedebfbf0f6572e19ca5c58a3f71 upstream.
We forgot to add the status bit for the PLLs and we were using
the wrong register and masks for configuration, leading to
unexpected PLL configurations. Fix this.
Fixes: d8b212014e69 (clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC))
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/clk/qcom/mmcc-msm8974.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c index c95774514b81..6a0ae77d1939 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -169,6 +169,7 @@ static struct clk_pll mmpll0 = { .config_reg = 0x0014, .mode_reg = 0x0000, .status_reg = 0x001c, + .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll0", .parent_names = (const char *[]){ "xo" }, @@ -192,9 +193,10 @@ static struct clk_pll mmpll1 = { .l_reg = 0x0044, .m_reg = 0x0048, .n_reg = 0x004c, - .config_reg = 0x0054, + .config_reg = 0x0050, .mode_reg = 0x0040, .status_reg = 0x005c, + .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll1", .parent_names = (const char *[]){ "xo" }, @@ -218,7 +220,7 @@ static struct clk_pll mmpll2 = { .l_reg = 0x4104, .m_reg = 0x4108, .n_reg = 0x410c, - .config_reg = 0x4114, + .config_reg = 0x4110, .mode_reg = 0x4100, .status_reg = 0x411c, .clkr.hw.init = &(struct clk_init_data){ @@ -233,9 +235,10 @@ static struct clk_pll mmpll3 = { .l_reg = 0x0084, .m_reg = 0x0088, .n_reg = 0x008c, - .config_reg = 0x0094, + .config_reg = 0x0090, .mode_reg = 0x0080, .status_reg = 0x009c, + .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll3", .parent_names = (const char *[]){ "xo" }, @@ -2318,7 +2321,7 @@ static const struct pll_config mmpll1_config = { .vco_val = 0x0, .vco_mask = 0x3 << 20, .pre_div_val = 0x0, - .pre_div_mask = 0x3 << 12, + .pre_div_mask = 0x7 << 12, .post_div_val = 0x0, .post_div_mask = 0x3 << 8, .mn_ena_mask = BIT(24), @@ -2332,7 +2335,7 @@ static struct pll_config mmpll3_config = { .vco_val = 0x0, .vco_mask = 0x3 << 20, .pre_div_val = 0x0, - .pre_div_mask = 0x3 << 12, + .pre_div_mask = 0x7 << 12, .post_div_val = 0x0, .post_div_mask = 0x3 << 8, .mn_ena_mask = BIT(24), |