diff options
| author | Stefan Agner <stefan@agner.ch> | 2014-03-05 23:11:08 +0100 |
|---|---|---|
| committer | Jiri Slaby <jslaby@suse.cz> | 2014-03-31 14:22:24 +0200 |
| commit | 07a2f05ccb2b392a0360653eb6f9d32906e2d516 (patch) | |
| tree | fff884b0e9d3cfbf364e59b8eeb3724007603d38 | |
| parent | aaaf6019ec191283b55b257deacc4c62ed9b26fb (diff) | |
clocksource: vf_pit_timer: use complement for sched_clock reading
commit 224aa3ed45c8735ae02bb2ecca002409fa6aa772 upstream.
Vybrids PIT register is monitonic decreasing. However, sched_clock
reading needs to be monitonic increasing. Use bitwise not to get
the complement of the clock register. This fixes the clock going
backward. Also, the clock now starts at 0 since we load the
register with the maximum value at start.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Cc: daniel.lezcano@linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Link: http://lkml.kernel.org/r/d25af915993aec1b486be653eb86f748ddef54fe.1394057313.git.stefan@agner.ch
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
| -rw-r--r-- | drivers/clocksource/vf_pit_timer.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c index 587e0202a70b..e5590953630e 100644 --- a/drivers/clocksource/vf_pit_timer.c +++ b/drivers/clocksource/vf_pit_timer.c @@ -54,7 +54,7 @@ static inline void pit_irq_acknowledge(void) static unsigned int pit_read_sched_clock(void) { - return __raw_readl(clksrc_base + PITCVAL); + return ~__raw_readl(clksrc_base + PITCVAL); } static int __init pit_clocksource_init(unsigned long rate) |