diff options
| author | Yu Zhao <yu.zhao@intel.com> | 2009-02-25 13:15:52 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2009-05-02 10:25:03 -0700 |
| commit | 7b91b355a659bba2075a6ce44e7cc79a45d31132 (patch) | |
| tree | ba891c37708c82bc9e750c3a5cb7fe839cd5ede2 | |
| parent | 0f6e7a29d6a4865951b8ae598fb5594a6eb54b54 (diff) | |
PCI: fix incorrect mask of PM No_Soft_Reset bit
commit 998dd7c719f62dcfa91d7bf7f4eb9c160e03d817 upstream.
Reviewed-by: Matthew Wilcox <matthew@wil.cx>
Signed-off-by: Yu Zhao <yu.zhao@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| -rw-r--r-- | include/linux/pci_regs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 450684f7eaac..f5cd0506b8f0 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -234,7 +234,7 @@ #define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ #define PCI_PM_CTRL 4 /* PM control and status register */ #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ -#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */ +#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */ #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ |