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authorEmanuele Ghidoli <emanuele.ghidoli@toradex.com>2023-01-04 15:04:12 +0100
committerMax Krummenacher <max.krummenacher@toradex.com>2024-03-26 19:24:22 +0100
commit7b000d1f6a1187759be81978f8278d846e557b73 (patch)
treec54598f44e43ec2caf55c8511bed9a36ed2212e3
parent68227dec8d0c842de91000784c81f74f860e58c3 (diff)
ASoC: nau8822: add speaker Bridge Tied Output configuration
Allow configuring the two loudspeaker outputs as a single Bridge Tied Load output getting higher output power. Upstream-Status: Backport [968b42069fe5dab362b623c6b8a1565709a12f5b] Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20230104140412.35575-4-francesco@dolcini.it Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/codecs/nau8822.c9
-rw-r--r--sound/soc/codecs/nau8822.h9
2 files changed, 18 insertions, 0 deletions
diff --git a/sound/soc/codecs/nau8822.c b/sound/soc/codecs/nau8822.c
index cd5053cfd521..85a85d043f6f 100644
--- a/sound/soc/codecs/nau8822.c
+++ b/sound/soc/codecs/nau8822.c
@@ -1059,6 +1059,7 @@ static const int update_reg[] = {
static int nau8822_probe(struct snd_soc_component *component)
{
int i;
+ struct device_node *of_node = component->dev->of_node;
/*
* Set the update bit in all registers, that have one. This way all
@@ -1069,6 +1070,14 @@ static int nau8822_probe(struct snd_soc_component *component)
snd_soc_component_update_bits(component,
update_reg[i], 0x100, 0x100);
+ /* Check property to configure the two loudspeaker outputs as
+ * a single Bridge Tied Load output
+ */
+ if (of_property_read_bool(of_node, "nuvoton,spk-btl"))
+ snd_soc_component_update_bits(component,
+ NAU8822_REG_RIGHT_SPEAKER_CONTROL,
+ NAU8822_RSUBBYP, NAU8822_RSUBBYP);
+
return 0;
}
diff --git a/sound/soc/codecs/nau8822.h b/sound/soc/codecs/nau8822.h
index 547ec057f853..646f6bb64bc5 100644
--- a/sound/soc/codecs/nau8822.h
+++ b/sound/soc/codecs/nau8822.h
@@ -187,6 +187,15 @@
/* NAU8822_REG_PLL_K3 (0x27) */
#define NAU8822_PLLK3_MASK 0x1FF
+/* NAU8822_REG_RIGHT_SPEAKER_CONTROL (0x2B) */
+#define NAU8822_RMIXMUT 0x20
+#define NAU8822_RSUBBYP 0x10
+
+#define NAU8822_RAUXRSUBG_SFT 1
+#define NAU8822_RAUXRSUBG_MASK 0x0E
+
+#define NAU8822_RAUXSMUT 0x01
+
/* System Clock Source */
enum {
NAU8822_CLK_MCLK,