diff options
| author | Dasnavis Sabiya <sabiya.d@ti.com> | 2024-03-15 17:18:20 +0530 |
|---|---|---|
| committer | Udit Kumar <u-kumar1@ti.com> | 2024-03-19 20:25:08 +0530 |
| commit | 7445094c7cfde396f2c2dd49599f357be86c35ac (patch) | |
| tree | 0df7ebb1926c3e3ec2410b1cf3494af62a0363bd | |
| parent | d0d3c1e91c7affc0a4c30793a93ba920076130ec (diff) | |
arm64: dts: ti: k3-am69-sk: Update Serdes0 to support Multilink PCIe configuration
AM69-SK has a 2 Lane PCIe M.2 Key M PCIe instance (PCIe1) and a 1 Lane
PCIe M.2 Key E PCIe instance (PCIe3), both of which are interfaced via a
shared Serdes instance namely Serdes0. Update the Serdes0 link to enable
Multilink PCIe configuration.
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am69-sk.dts | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index c23e827b168c..444bb05c11d8 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -728,12 +728,19 @@ &serdes0 { status = "okay"; - serdes0_pcie_link: phy@0 { + serdes0_pcie_link1: phy@0 { reg = <0>; - cdns,num-lanes = <3>; + cdns,num-lanes = <2>; #phy-cells = <0>; cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + serdes0_pcie_link2: phy@2 { + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 3>; }; serdes0_usb_link: phy@3 { reg = <3>; @@ -775,14 +782,14 @@ &pcie1_rc { status = "okay"; reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; + phys = <&serdes0_pcie_link1>; phy-names = "pcie-phy"; num-lanes = <2>; }; &pcie1_ep { status = "disabled"; - phys = <&serdes0_pcie_link>; + phys = <&serdes0_pcie_link1>; phy-names = "pcie-phy"; num-lanes = <2>; }; @@ -790,14 +797,14 @@ &pcie3_rc { status = "okay"; reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; + phys = <&serdes0_pcie_link2>; phy-names = "pcie-phy"; num-lanes = <1>; }; &pcie3_ep { status = "disabled"; - phys = <&serdes0_pcie_link>; + phys = <&serdes0_pcie_link2>; phy-names = "pcie-phy"; num-lanes = <1>; }; |