diff options
| author | Ravi Gunasekaran <r-gunasekaran@ti.com> | 2024-03-12 15:56:56 +0530 |
|---|---|---|
| committer | Praneeth Bajjuri <praneeth@ti.com> | 2024-03-12 15:51:03 -0500 |
| commit | 4670156ee7073e890934851fb43d429bb868892c (patch) | |
| tree | 1611b4a871f096b4eb86eb3cee7299ff14d6f372 | |
| parent | 7596cf0da0653c3a44ae25c6bdbd39ba3e7a96e3 (diff) | |
arm64: dts: ti: k3-am64-main: Switch ICSSG core clock to 333MHz
In order to fully to support all the HSR offload features at 1G,
more clock cycles are needed. So switch the ICSSG core clock from
250MHz to 333MHz.
This switch to 333MHz is applicable for all 3 modes - MAC mode,
Switch Mode and HSR Mode and improves performance as well.
Performance update in dual mac mode
With Core Clk @ 333MHz
Tx throughput - 934 Mbps
Rx throuhput - 914 Mbps,
With core clk @ 250MHz,
Tx throughput - 920 Mbps
Rx throughput - 706 Mbps
The improvement in performance is in alignment with the firmware
team's understanding that Rx budget cycle is tight at 250MHz.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index ecf1a50f197c..2bf45e8dfde3 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1093,6 +1093,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x30000000 0x80000>; + assigned-clocks = <&k3_clks 81 0>; + assigned-clock-parents = <&k3_clks 81 2>; icssg0_mem: memories@0 { reg = <0x0 0x2000>, @@ -1118,7 +1120,7 @@ clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ <&k3_clks 81 20>; /* icssg0_iclk */ assigned-clocks = <&icssg0_coreclk_mux>; - assigned-clock-parents = <&k3_clks 81 20>; + assigned-clock-parents = <&k3_clks 81 0>; }; icssg0_iepclk_mux: iepclk-mux@30 { @@ -1263,6 +1265,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x30080000 0x80000>; + assigned-clocks = <&k3_clks 82 0>; + assigned-clock-parents = <&k3_clks 82 2>; icssg1_mem: memories@0 { reg = <0x0 0x2000>, @@ -1288,7 +1292,7 @@ clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ <&k3_clks 82 20>; /* icssg1_iclk */ assigned-clocks = <&icssg1_coreclk_mux>; - assigned-clock-parents = <&k3_clks 82 20>; + assigned-clock-parents = <&k3_clks 82 0>; }; icssg1_iepclk_mux: iepclk-mux@30 { |