fsl-imx8qxp-colibri-eval-v3.dts: sync with fsl-imx8qxp-mek.dtsi

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>

1 files changed, 133 insertions, 56 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts
index 4753d7416a0a..7e74e35c4a66 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts
@@ -220,14 +220,14 @@
 			fsl,pins = <
 				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
 				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
-				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000060
-				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000060
-				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000060
-				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000060
-				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000060
-				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000060
-				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000060
-				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x06000060
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x00000061
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000061
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000061
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000061
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000061
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000061
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x00000061
 			>;
 		};
 
@@ -235,14 +235,14 @@
 			fsl,pins = <
 				SC_P_ENET0_MDC_LSIO_GPIO5_IO11			0x06000041
 				SC_P_ENET0_MDIO_LSIO_GPIO5_IO10			0x06000041
-				SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30		0x06000041
-				SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29		0x06000041
-				SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31		0x06000041
-				SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00		0x06000041
-				SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04		0x06000041
-				SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05		0x06000041
-				SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06		0x06000041
-				SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07		0x06000041
+				SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30		0x00000041
+				SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29		0x00000041
+				SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31		0x00000041
+				SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00		0x00000041
+				SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04		0x00000041
+				SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05		0x00000041
+				SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06		0x00000041
+				SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07		0x00000041
 			>;
 		};
 
@@ -417,35 +417,35 @@
 
 		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 			fsl,pins = <
-				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
-				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
-				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
-				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
-				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
-				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
-				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
-				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
-				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
-				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
-				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
 			>;
 		};
 
 		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 			fsl,pins = <
-				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
-				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
-				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
-				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
-				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
-				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
-				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
-				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
-				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
-				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
-				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
 			>;
 		};
 
@@ -469,25 +469,25 @@
 
 		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 			fsl,pins = <
-				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
 			>;
 		};
 
 		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 			fsl,pins = <
-				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
 			>;
 		};
 #if 0
@@ -619,6 +619,83 @@
 	status = "okay";
 };
 
+&pixel_combiner {
+	status = "okay";
+};
+
+&prg1 {
+	status = "okay";
+};
+
+&prg2 {
+	status = "okay";
+};
+
+&prg3 {
+	status = "okay";
+};
+
+&prg4 {
+	status = "okay";
+};
+
+&prg5 {
+	status = "okay";
+};
+
+&prg6 {
+	status = "okay";
+};
+
+&prg7 {
+	status = "okay";
+};
+
+&prg8 {
+	status = "okay";
+};
+
+&prg9 {
+	status = "okay";
+};
+
+/* Display Prefetch Resolve, (Tiling) */
+&dpr1_channel1 {
+	status = "okay";
+};
+
+&dpr1_channel2 {
+	status = "okay";
+};
+
+&dpr1_channel3 {
+	status = "okay";
+};
+
+&dpr2_channel1 {
+	status = "okay";
+};
+
+&dpr2_channel2 {
+	status = "okay";
+};
+
+&dpr2_channel3 {
+	status = "okay";
+};
+
+&dpu1 {
+	status = "okay";
+};
+
+&gpu_3d0 {
+	status = "okay";
+};
+
+&imx8_gpu_ss {
+	status = "okay";
+};
+
 &fec1 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&pinctrl_fec1>;
@@ -832,8 +909,8 @@
 	/*
 	 * 64K for one rpmsg instance:
 	 */
-	vdev-nums = <1>;
-	reg = <0x0 0x90000000 0x0 0x10000>;
+	vdev-nums = <2>;
+	reg = <0x0 0x90000000 0x0 0x20000>;
 	status = "okay";
 };