diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-04-15 17:46:59 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-04-17 09:14:13 +0200 |
| commit | ba355c7617a5a59773626bc0afeaad6cc496cee8 (patch) | |
| tree | 5572e7379f124f4188ae11fc42a5a518c9960211 | |
| parent | 997ffd57a34ee7ab0df2b3cf4c62215671530e37 (diff) | |
ARM: dts: imx8: apalis-imx8qm: add gpio muxings
Add various GPIO muxings: CAM1, GPIO3/4/5/6, SATA1_ACT and WAKE1_MICO.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts | 61 |
1 files changed, 58 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts index cf7399aaf20b..1c83c487fd04 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts @@ -159,6 +159,9 @@ }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_gpio34>, <&pinctrl_gpio56>, <&pinctrl_sata1_act>, <&pinctrl_wake1_mico>; + apalis-imx8qm { pinctrl_sgtl5000: sgtl5000grp { fsl,pins = < @@ -176,6 +179,31 @@ >; }; + pinctrl_gpio34: gpio34grp { + fsl,pins = < + /* Apalis GPIO3 */ + SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 0x06000021 + /* Apalis GPIO4 */ + SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 0x06000021 + >; + }; + + pinctrl_gpio56: gpio56grp { + fsl,pins = < + /* Apalis GPIO5 */ + SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000021 + /* Apalis GPIO6 */ + SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x06000021 + >; + }; + + pinctrl_wake1_mico: wake1micogrp { + fsl,pins = < + /* Apalis WAKE1_MICO */ + SC_P_SPI3_CS0_LSIO_GPIO2_IO20 0x06000021 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 @@ -223,12 +251,32 @@ >; }; - pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + pinctrl_cam1_gpios: cam1gpiosgrp { fsl,pins = < /* Apalis CAM1_D7 */ - SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c + SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021 /* Apalis CAM1_D6 */ - SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c + SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021 + /* Apalis CAM1_D5 */ + SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 0x00000021 + /* Apalis CAM1_D4 */ + SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 0x00000021 + /* Apalis CAM1_D3 */ + SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x00000021 + /* Apalis CAM1_D2 */ + SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 0x00000021 + /* Apalis CAM1_D1 */ + SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x00000021 + /* Apalis CAM1_D0 */ + SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 0x00000021 + /* Apalis CAM1_PCLK */ + SC_P_MCLK_IN0_LSIO_GPIO3_IO00 0x00000021 + /* Apalis CAM1_MCLK */ + SC_P_SPI3_SDO_LSIO_GPIO2_IO18 0x00000021 + /* Apalis CAM1_HSYNC */ + SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 0x00000021 + /* Apalis CAM1_VSYNC */ + SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 0x00000021 >; }; @@ -382,6 +430,13 @@ >; }; + pinctrl_sata1_act: sata1actgrp { + fsl,pins = < + /* Apalis SATA1_ACT# */ + SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021 + >; + }; + pinctrl_mmc1_cd: mmc1cdgrp { fsl,pins = < /* Apalis MMC1_CD# */ |