diff options
| author | Stefan Eichenberger <stefan.eichenberger@toradex.com> | 2023-03-27 16:41:13 +0200 |
|---|---|---|
| committer | Stefan Eichenberger <eichest@gmail.com> | 2023-04-21 08:53:44 +0200 |
| commit | c28f954b83297664b541cd79d121ab4508c0f7ff (patch) | |
| tree | 70a6e8117ff446918fa2cfe59ad9b8583a3cf5f0 | |
| parent | bff49426d39075172fceb9b32b8da1d1b430d573 (diff) | |
arm64: dts: imx8-apalis: use the hsio clocks for pcie and sata
Use the hsio clocks for pcie and sata as NXP does in their device tree.
We can therefore remove the pcie_ext and sata_ext properties and don't
have to add any special properties.
Upstream-Status: Pending
Mainline for i.MX 8 does not support PCIe yet, this patch cannot be
upstreamed as of now.
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi | 35 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi | 8 |
2 files changed, 13 insertions, 30 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index b2608413912f..7fabc691b43b 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -43,18 +43,6 @@ }; }; - pcie_sata_refclk_gate: sata-ref-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pcie_wifi_refclk_gate: wifi-ref-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - /* * Power management bus used to control LDO1OUT of the * second PMIC PF8100. This is used for controlling voltage levels of @@ -412,6 +400,11 @@ enable-gpios = <&lsio_gpio2 11 GPIO_ACTIVE_HIGH>; }; +&phyx2_lpcg { + clocks = <&hsio_refa_clk>, <&hsio_refb_clk>, + <&hsio_refa_clk>, <&hsio_per_clk>; +}; + /* On-module I2C */ &i2c1 { #address-cells = <1>; @@ -829,11 +822,9 @@ <&phyx2_lpcg 0>, <&phyx2_crr0_lpcg 0>, <&pciea_crr2_lpcg 0>, - <&misc_crr5_lpcg 0>, - <&pcie_sata_refclk_gate>; + <&misc_crr5_lpcg 0>; clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", - "pcie_phy", "phy_per", "pcie_per", "misc_per", - "pcie_ext"; + "pcie_phy", "phy_per", "pcie_per", "misc_per"; ext_osc = <1>; fsl,max-link-speed = <1>; pinctrl-names = "default"; @@ -852,12 +843,10 @@ <&phyx2_crr0_lpcg 0>, <&pcieb_crr3_lpcg 0>, <&pciea_crr2_lpcg 0>, - <&misc_crr5_lpcg 0>, - <&pcie_wifi_refclk_gate>; + <&misc_crr5_lpcg 0>; clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", "pcie_phy", "pcie_phy_pclk", "phy_per", - "pcie_per", "pciex2_per", "misc_per", - "pcie_ext"; + "pcie_per", "pciex2_per", "misc_per"; epdev_on-supply = <®_module_wifi>; ext_osc = <1>; fsl,max-link-speed = <1>; @@ -900,13 +889,11 @@ <&misc_crr5_lpcg 0>, <&phyx2_lpcg 0>, <&phyx2_lpcg 1>, - <&phyx1_lpcg 3>, - <&pcie_sata_refclk_gate>; + <&phyx1_lpcg 3>; clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", "per_clk0", "per_clk1", "per_clk2", "per_clk3", "per_clk4", "per_clk5", - "phy_pclk0", "phy_pclk1", "phy_apbclk", - "sata_ext"; + "phy_pclk0", "phy_pclk1", "phy_apbclk"; ext_osc = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi index 6eeded385a76..e038598d65d0 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi @@ -11,8 +11,6 @@ "fsl,imx8qm"; }; -/delete-node/ &pcie_wifi_refclk_gate; - ðphy0 { interrupts = <5 IRQ_TYPE_LEVEL_LOW>; }; @@ -332,12 +330,10 @@ <&phyx2_crr0_lpcg 0>, <&pcieb_crr3_lpcg 0>, <&pciea_crr2_lpcg 0>, - <&misc_crr5_lpcg 0>, - <&pcie_sata_refclk_gate>; + <&misc_crr5_lpcg 0>; clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", "pcie_phy", "pcie_phy_pclk", "phy_per", - "pcie_per", "pciex2_per", "misc_per", - "pcie_ext"; + "pcie_per", "pciex2_per", "misc_per"; }; /* Apalis MMC1 */ |