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authorStefan Eichenberger <stefan.eichenberger@toradex.com>2023-04-19 09:57:39 +0200
committerStefan Eichenberger <eichest@gmail.com>2023-04-21 08:53:45 +0200
commit9068c0de533b21b5e858f953ca813a4d5a1b2d22 (patch)
tree275bcaf5926b647cadf71a115f3a4761dce5d84e
parent359c86bcbf6a1b483183121c1d8a9de878ef67d1 (diff)
arm64: dts: imx8-apalis: remove redundant clocks from pcie and sata
We set the same pcie and sata clock as the include files. This commit removes redundancy. Upstream-Status: Pending Mainline for i.MX 8 does not support PCIe yet, this patch cannot be upstreamed as of now. Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
-rw-r--r--arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi38
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi16
2 files changed, 0 insertions, 54 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
index 249bf01068f0..2781a9f78d8a 100644
--- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
@@ -816,15 +816,6 @@
/* Apalis PCIE1 */
&pciea {
- clocks = <&pciea_lpcg 0>,
- <&pciea_lpcg 1>,
- <&pciea_lpcg 2>,
- <&phyx2_lpcg 0>,
- <&phyx2_crr0_lpcg 0>,
- <&pciea_crr2_lpcg 0>,
- <&misc_crr5_lpcg 0>;
- clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
- "pcie_phy", "phy_per", "pcie_per", "misc_per";
ext_osc = <1>;
fsl,max-link-speed = <1>;
pinctrl-names = "default";
@@ -835,18 +826,6 @@
/* On-module Wi-Fi */
&pcieb {
- clocks = <&pcieb_lpcg 0>,
- <&pcieb_lpcg 1>,
- <&pcieb_lpcg 2>,
- <&phyx2_lpcg 1>,
- <&phyx2_lpcg 0>,
- <&phyx2_crr0_lpcg 0>,
- <&pcieb_crr3_lpcg 0>,
- <&pciea_crr2_lpcg 0>,
- <&misc_crr5_lpcg 0>;
- clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
- "pcie_phy", "pcie_phy_pclk", "phy_per",
- "pcie_per", "pciex2_per", "misc_per";
vpcie-supply = <&reg_module_wifi>;
ext_osc = <1>;
fsl,max-link-speed = <1>;
@@ -877,23 +856,6 @@
/* Apalis SATA1 */
&sata {
- clocks = <&sata_lpcg 0>,
- <&phyx1_lpcg 0>,
- <&phyx1_lpcg 1>,
- <&phyx1_lpcg 2>,
- <&phyx2_crr0_lpcg 0>,
- <&phyx1_crr1_lpcg 0>,
- <&pciea_crr2_lpcg 0>,
- <&pcieb_crr3_lpcg 0>,
- <&sata_crr4_lpcg 0>,
- <&misc_crr5_lpcg 0>,
- <&phyx2_lpcg 0>,
- <&phyx2_lpcg 1>,
- <&phyx1_lpcg 3>;
- clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx",
- "per_clk0", "per_clk1", "per_clk2",
- "per_clk3", "per_clk4", "per_clk5",
- "phy_pclk0", "phy_pclk1", "phy_apbclk";
ext_osc = <1>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
index e038598d65d0..a5d1167d0ba8 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
@@ -320,22 +320,6 @@
<IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021>;
};
-/* On-module Wi-Fi */
-&pcieb {
- clocks = <&pcieb_lpcg 0>,
- <&pcieb_lpcg 1>,
- <&pcieb_lpcg 2>,
- <&phyx2_lpcg 1>,
- <&phyx2_lpcg 0>,
- <&phyx2_crr0_lpcg 0>,
- <&pcieb_crr3_lpcg 0>,
- <&pciea_crr2_lpcg 0>,
- <&misc_crr5_lpcg 0>;
- clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
- "pcie_phy", "pcie_phy_pclk", "phy_per",
- "pcie_per", "pciex2_per", "misc_per";
-};
-
/* Apalis MMC1 */
&usdhc2 {
/*