diff options
| author | Philippe Schenker <philippe.schenker@toradex.com> | 2022-07-28 19:16:20 +0200 |
|---|---|---|
| committer | Philippe Schenker <philippe.schenker@toradex.com> | 2022-07-29 11:41:54 +0200 |
| commit | c5c03f5d0e2e0abe602dc6c7a7911426bec918ea (patch) | |
| tree | a8f81b8e71609cb26d48f48e5f9b31cf0ff3b51f | |
| parent | 0059b164d450168506e0cabe62f95da74bf526c5 (diff) | |
arm64: dts: imx8mm-verdin: adjust pcie to downstream
On the downstream kernel it has to be differently setup how the PCIe
clock is being derived. Use the opposite of ext_osc what the NXP evk uses.
Add clocks that are also used on imx8mm-evk.dtsi.
Upstream-Status: Inappropriate [other]
- Commit only needed for NXP downstream kernel
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index d1b4582f44c4..63899b97309f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -3,7 +3,6 @@ * Copyright 2022 Toradex */ -#include "dt-bindings/phy/phy-imx8-pcie.h" #include "dt-bindings/pwm/pwm.h" #include "imx8mm.dtsi" @@ -53,6 +52,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + /* Carrier Board Supplies */ reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; @@ -634,13 +639,16 @@ /* Verdin PCIE_1 */ &pcie0 { assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_100M>, <&clk IMX8MM_SYS_PLL2_250M>; - assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_PHY>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; + <&clk IMX8MM_CLK_PCIE1_PHY>, <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + ext_osc = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; /* PCIE_1_RESET# (SODIMM 244) */ @@ -649,8 +657,6 @@ &pcie_phy { clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; - fsl,clkreq-unsupported; - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; fsl,tx-deemph-gen1 = <0x2d>; fsl,tx-deemph-gen2 = <0xf>; }; |