diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2022-08-29 17:12:40 +0200 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2022-09-21 19:13:39 +0200 |
| commit | 7653f2156ae2ab8bc1e58b53dca1f55101228d80 (patch) | |
| tree | 4f9557dfccb936a4326836b1dee1a834ed007a21 | |
| parent | f7336b9a2f057ee8a07953fb1eacc12251f1f3ae (diff) | |
arm64: dts: imx8mp-verdin: add pcie functionality
Enable the PCIe and PCIe PHY.
Upstream-status: Pending [mainline does not support PCIe yet]
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi | 10 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 25 |
2 files changed, 33 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index bb3ac603ad7b..48ef964eb621 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -109,7 +109,15 @@ }; }; -/* TODO: Verdin PCIE_1 */ +/* Verdin PCIE_1 */ +&pcie { + epdev_on-supply = <®_3p3v>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; /* Verdin PWM_1 */ &pwm1 { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index b90fa8fd5d37..89a0924faabe 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -827,7 +827,30 @@ }; }; -/* TODO: Verdin PCIE_1 */ +/* Verdin PCIE_1 */ +&pcie { + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <500000000>, <10000000>; + bus-range = <0x00 0xff>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_PCIE_AUX>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + ext_osc = <0>; + l1ss-disabled; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + /* PCIE_1_RESET# (SODIMM 244) */ + reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; +}; + +&pcie_phy { + ext_osc = <0>; +}; /* Verdin PWM_1 */ &pwm1 { |