diff options
| author | Krishna Reddy <vdumpa@nvidia.com> | 2015-04-06 11:30:13 -0700 |
|---|---|---|
| committer | Matthew Pedro <mapedro@nvidia.com> | 2015-05-14 10:01:09 -0700 |
| commit | dff43e9bd5fa489306fdd7fcdbe720b54df5e675 (patch) | |
| tree | 7533c48b267bc9b9b3c568c02ace0fcb10b9995b | |
| parent | eab8bc165cd104e59be4bc960b7d1019b79e4979 (diff) | |
arm64: mm: Add __clean_dcache_louis
This allows perform L1 cache clean alone.
Bug 200077334
Change-Id: I776de6e6726862e330b626fd19f8ae8f70055538
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/742254
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
| -rw-r--r-- | arch/arm64/mm/cache.S | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index e64b6d8405e9..334d4f90c9b4 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -103,6 +103,21 @@ ENTRY(__clean_dcache_all) ENDPROC(__clean_dcache_all) /* + * __clean_dcache_louis() + * + * Clean D-cache to the level of unification inner shareable + * + * Corrupted registers: x0-x7, x9-x11 + */ +ENTRY(__clean_dcache_louis) + dsb sy // ensure ordering with previous memory accesses + mrs x0, clidr_el1 // read clidr + and x3, x0, #0xe00000 // extract louis from clidr + lsr x3, x3, #20 // left align louis bit field + v8_op_dcache_all csw +ENDPROC(__clean_dcache_louis) + +/* * flush_cache_all() * * Flush the entire cache system. The data cache flush is now achieved |