summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorArun Kannan <akannan@nvidia.com>2015-05-11 17:15:45 -0700
committerMatthew Pedro <mapedro@nvidia.com>2015-06-01 14:49:59 -0700
commit96bd245219fa083d790372b656ce8ce0946990e0 (patch)
treecb53489d9a5eca2f72f88702e0bad267ac91dfef
parent120e8796ffbdcaa979a22de71b2036a64d924b08 (diff)
video: tegra: host: pod: change vic freq tuning
Tune nvhost_podgov scaling algo params for vic03 frequency scaling. Bug 1640539 Change-Id: Id5583b5cd60d6b4449470d8c3df1e5d06bc4aedb Signed-off-by: Arun Kannan <akannan@nvidia.com> Reviewed-on: http://git-master/r/741438 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Kamal Balagopalan <kbalagopalan@nvidia.com> Reviewed-by: Ming Wong <miwong@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
-rw-r--r--drivers/video/tegra/host/pod_scaling.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/video/tegra/host/pod_scaling.c b/drivers/video/tegra/host/pod_scaling.c
index 64898950bab5..7ece923321eb 100644
--- a/drivers/video/tegra/host/pod_scaling.c
+++ b/drivers/video/tegra/host/pod_scaling.c
@@ -3,7 +3,7 @@
*
* Tegra Graphics Host 3D clock scaling
*
- * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -839,15 +839,15 @@ static int nvhost_pod_init(struct devfreq *df)
podgov->p_use_throughput_hint = 1;
if (!strcmp(d->name, "vic03.0")) {
- podgov->p_load_max = 990;
- podgov->p_load_target = 800;
+ podgov->p_load_max = 100;
+ podgov->p_load_target = 10;
podgov->p_bias = 80;
podgov->p_hint_lo_limit = 500;
podgov->p_hint_hi_limit = 997;
podgov->p_scaleup_limit = 1100;
podgov->p_scaledown_limit = 1300;
- podgov->p_smooth = 10;
- podgov->p_damp = 7;
+ podgov->p_smooth = 30;
+ podgov->p_damp = 9;
} else {
switch (cid) {
case TEGRA_CHIPID_TEGRA14: