[ARM/tegra] nvrm_i2c: provide valid APB address for I2C DMA

the DMA API expects that the peripheral address supplied by the client
is a valid APB address in the system memory map (0x7000:xxxx); however,
the I2C code was only providing the offset of the register relative
to the start of the controller's aperture.

it's not clear how this ever worked, but the additional error checking
in the new RM DMA-on-native DMA implementation choked on this, highlighting
the problem

Change-Id: I4e10be05e03a6feeff4b0a26b5f870caf9ee5e1c
Reviewed-on: http://git-master/r/2017
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>

3 files changed, 8 insertions, 2 deletions

diff --git a/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_i2c.c b/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_i2c.c
index c9d40286704b..292111035fe3 100644
--- a/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_i2c.c
+++ b/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_i2c.c
@@ -1497,13 +1497,13 @@ NvError AP20RmI2cOpen(NvRmI2cControllerHandle hRmI2cCont)
     {
         hRmI2cCont->DmaBufferSize = DEFAULT_I2C_DMA_BUFFER_SIZE;
         
-        hRmI2cCont->RxDmaReq.SourceBufferPhyAddress= RxFifoPhyAddress;
+        hRmI2cCont->RxDmaReq.SourceBufferPhyAddress= RxFifoPhyAddress + hRmI2cCont->ControllerAdd;
         hRmI2cCont->RxDmaReq.DestinationBufferPhyAddress = hRmI2cCont->DmaBuffPhysAdd;
         hRmI2cCont->RxDmaReq.SourceAddressWrapSize = 4;
         hRmI2cCont->RxDmaReq.DestinationAddressWrapSize = 0;
         
         hRmI2cCont->TxDmaReq.SourceBufferPhyAddress= hRmI2cCont->DmaBuffPhysAdd;
-        hRmI2cCont->TxDmaReq.DestinationBufferPhyAddress = TxFifoPhyAddress;
+        hRmI2cCont->TxDmaReq.DestinationBufferPhyAddress = TxFifoPhyAddress + hRmI2cCont->ControllerAdd;
         hRmI2cCont->TxDmaReq.SourceAddressWrapSize = 0;
         hRmI2cCont->TxDmaReq.DestinationAddressWrapSize = 4;
     }
diff --git a/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c.c b/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c.c
index bfc37c1d2a11..d4eca1c6cd5f 100644
--- a/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c.c
+++ b/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c.c
@@ -213,6 +213,7 @@ NvRmI2cOpen(
     // If no clients are opened yet, initialize the i2c controller
     if (c->NumberOfClientsOpened == 0)
     {
+        NvU32 len;
         /* Polulate the controller structure */
         c->hRmDevice = hRmDevice;
         c->OdmIoModule = IoModule;
@@ -228,6 +229,8 @@ NvRmI2cOpen(
         c->hSclPin = 0;
         c->hSdaPin = 0;
 
+        NvRmModuleGetBaseAddress(hRmDevice, NVRM_MODULE_ID(ModuleID, instance),
+            &c->ControllerAdd, &len);
 
         I2cGetSocCapabilities(hRmDevice, ModuleID, instance, &(c->SocI2cCaps));
         c->EnableNewMaster = c->SocI2cCaps.IsNewMasterAvailable;
diff --git a/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c_private.h b/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c_private.h
index e7af0aa7c09c..668391497a22 100644
--- a/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c_private.h
+++ b/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c_private.h
@@ -211,6 +211,9 @@ typedef struct NvRmI2cControllerRec
     // Dma buffer physical address.
     NvRmPhysAddr DmaBuffPhysAdd;
 
+    // Controller physical address
+    NvRmPhysAddr ControllerAdd;
+
     // Virtual pointer to the dma buffer.
     NvU32 *pDmaBuffer;