tegra usb: Modified UTMIP regs to prevent electrical test failures.

Summary of changes to AP20 USB PHY:
1. UTMIP_XCVR_CFG0:
a. UTMIP_XCVR_SETUP field is being set to 0x9. Its programming through
fuses is disabled.
b. UTMIP_XCVR_HSSLEW_MSB field is programmed to 0 for non-host mode.
Its default value on reset is 1.

2. UTMIP_HSRX_CFG1: UTMIP_HS_SYNC_START_DLY field is now set to 0.
Previously it was 9.

3. UTMIP_TX_CFG0: Removed programming of UTMIP_FS_PREAMBLE_J field to 1.
It should be 0 which is its default value.

4. UTMIP_SPARE_CFG0: Removed programming of this reg since now it is not
required to read fuses to obtain value for UTMIP_XCVR_SETUP field.

5. UTMIP_XCVR_CFG1: Programming UTMIP_XCVR_TERM_RANGE_ADJ field to 0x6.

Bug 672008: AP20: USB3_UTMIP electrical parameters cause physical-level
failures

Change-Id: Idadff030d49584b25678179b876ab200f670af21
Reviewed-on: http://git-master/r/1198
Tested-by: Abhishek Aggarwal <aaggarwal@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

1 files changed, 16 insertions, 9 deletions

diff --git a/arch/arm/mach-tegra/nvddk/nvddk_usbphy_ap20.c b/arch/arm/mach-tegra/nvddk/nvddk_usbphy_ap20.c
index 57a72b625d6a..159873da6aca 100644
--- a/arch/arm/mach-tegra/nvddk/nvddk_usbphy_ap20.c
+++ b/arch/arm/mach-tegra/nvddk/nvddk_usbphy_ap20.c
@@ -272,7 +272,7 @@ static const NvU8 s_UtmipIdleWaitDelay    = 17;
 //UTMIP Elastic limit
 static const NvU8 s_UtmipElasticLimit     = 16;
 //UTMIP High Speed Sync Start Delay
-static const NvU8 s_UtmipHsSyncStartDelay = 9;
+static const NvU8 s_UtmipHsSyncStartDelay = 0;
 
 
 static NvError
@@ -317,8 +317,6 @@ Ap20UsbPhyUtmiConfigure(
         USB1_IF_REG_WR(USB1_LEGACY_CTRL, RegVal);
     }
 
-    USB_UTMIP_REG_UPDATE_NUM(TX_CFG0, UTMIP_FS_PREAMBLE_J, 0x1);
-
     // Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
     // Setting these fields, together with default values of the other
     // fields, results in programming the registers below as follows:
@@ -368,7 +366,13 @@ Ap20UsbPhyUtmiPowerControl(
     NvBool Enable)
 {
     NvU32 RegVal = 0;
-    NvU32 XcvrSetupValue = 0x8; 
+
+    /* UTMIP_XCVR_SETUP setting of 0x9, in conjunction with
+       UTMIP_XCVR_TERM_RANGE_ADJ of 0x6, gives the maximum guard band around
+       the USB electrical spec. This is true across fast and slow chips, high
+       and low voltage, and hot and cold temperature. */
+    NvU32 XcvrSetupValue = 0x9;
+    NvU32 XcvrTermRangeAdj = 0x6;
 
     if (Enable)
     {
@@ -409,12 +413,13 @@ Ap20UsbPhyUtmiPowerControl(
             RegVal = USB_UTMIP_FLD_SET_DRF_DEF(
                         XCVR_CFG0, UTMIP_XCVR_LSRSLEW, 2, RegVal);
         }
-        USB_UTMIP_REG_WR(XCVR_CFG0, RegVal);
+        else
+        {
+            RegVal = USB_UTMIP_FLD_SET_DRF_DEF(
+                        XCVR_CFG0, UTMIP_XCVR_HSSLEW_MSB, 0, RegVal);
+        }
 
-        // Enables the PHY calibration values to read from the fuses.
-        RegVal = USB_UTMIP_REG_RD(SPARE_CFG0);
-        RegVal |= (1 << 3);
-        USB_UTMIP_REG_WR(SPARE_CFG0, RegVal);
+        USB_UTMIP_REG_WR(XCVR_CFG0, RegVal);
 
         RegVal = USB_UTMIP_REG_RD(XCVR_CFG1);
         RegVal = USB_UTMIP_FLD_SET_DRF_DEF(
@@ -423,6 +428,8 @@ Ap20UsbPhyUtmiPowerControl(
                     XCVR_CFG1, UTMIP_FORCE_PDCHRP_POWERDOWN, 0, RegVal);
         RegVal = USB_UTMIP_FLD_SET_DRF_DEF(
                     XCVR_CFG1, UTMIP_FORCE_PDDR_POWERDOWN, 0, RegVal);
+        RegVal = USB_UTMIP_FLD_SET_DRF_DEF(
+                    XCVR_CFG1, UTMIP_XCVR_TERM_RANGE_ADJ, XcvrTermRangeAdj, RegVal);
         USB_UTMIP_REG_WR(XCVR_CFG1, RegVal);
 
         // Enable Batery charge enabling bit, set to '0' for enable