diff options
| author | Mayuresh Kulkarni <mkulkarni@nvidia.com> | 2010-04-20 17:38:25 +0530 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-04-20 12:25:37 -0700 |
| commit | 18e28a34a902ba67ff7bd29c65722e270c8cd01d (patch) | |
| tree | 3aecd5e5c4abcddfc0d4060be8dcdbeb77a5e77a | |
| parent | f1801279d7f8480cb8643bf23b8306d2ea07219d (diff) | |
tegra pm: adding a delay of 2ms after writing to APBDEV_PMC_CNTRL_0
It seems that after writing SYSCLK_OE bit in APBDEV_PMC_CNTRL_0,
a delay needs to be added for stabilization.
Reviewed by Bharat. Tested on Harmony (A02, R04 EC firmware) for
multiple flash and reboot.
Bug 676490 - [T20/Harmony] Bootup failure on harmony-inconsistent (3/5 times)
Change-Id: I1f45a86aa23ac00b43f0103285cceda970ee5b39
Reviewed-on: http://git-master/r/1160
Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/power-t2.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/power-t2.c b/arch/arm/mach-tegra/power-t2.c index e340298cc5ae..44b47879f4a0 100644 --- a/arch/arm/mach-tegra/power-t2.c +++ b/arch/arm/mach-tegra/power-t2.c @@ -303,6 +303,7 @@ void power_lp0_init(void) //Enable clock request signal if supported and it's polarity. Reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, SYSCLK_OE, ENABLE, Reg); + if (PmuProperty.SysClockReqPolarity == NvOdmSysClockReqPolarity_Low) { Reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, @@ -310,6 +311,10 @@ void power_lp0_init(void) } NV_PMC_REGW(g_pPMC,CNTRL,Reg); + //Add a 2ms delay to ensure that writes to + //the control register (which is in the 32KHz domain) + //take place in-order. + NvOsWaitUS(2000); //Enable CORE power request output if it is connected separately //to PMU; keep it tristated if it is combined with CPU request - |