diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2010-04-09 17:15:09 -0700 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-04-11 10:29:41 -0700 |
| commit | a523de81339090270a2fbbede04904d77989d690 (patch) | |
| tree | f288aa55339f1eb7c6aa110d2ce2e737f9199df5 | |
| parent | e95fb51bc9488d618218b75d127628ba0ab14b86 (diff) | |
tegra: invalidate CPU state when starting secondary processor
tegra_secondary_startup was not invalidating the entire CPU state when
bringing up a slave CPU. This change adds invalidation of the I-cache,
TLB, and BTAC, and also enables the I-cache and branch prediction to speed
up D-cache invalidation.
Change-Id: I82b21dde7befb5ae634a72418b06892a30ec1ebf
Reviewed-on: http://git-master/r/1069
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/headsmp.S | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index ee6a0976d1ca..dadad41a2008 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -70,8 +70,17 @@ ENDPROC(v7_invalidate_l1) ENTRY(tegra_secondary_startup) msr cpsr_fsxc, #0xd3 + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate i-cache + mcr p15, 0, r0, c7, c5, 6 @ flusth btac + mcr p15, 0, r0, c8, c7, 0 @ invalidate unified TLBs + mcr p15, 0, r0, c7, c10, 4 @ dsb + mcr p15, 0, r0, c7, c5, 4 @ isb + mrc p15, 0, r0, c1, c0, 0 @ sctlr + orr r0, r0, #0x1800 @ sctlr.i | sctlr.z + mcr p15, 0, r0, c1, c0, 0 @ sctlr bl v7_invalidate_l1 - mrc p15, 0, r0, c0, c0, 5 + mrc p15, 0, r0, c0, c0, 5 @ mpidr and r0, r0, #15 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) ldr r1, =0x6000f100 |