diff options
| author | Luke Huang <lhuang@nvidia.com> | 2011-08-22 19:33:59 -0700 |
|---|---|---|
| committer | Ryan Wong <ryanw@nvidia.com> | 2011-08-22 20:17:03 -0700 |
| commit | 36c0621bcc288858345ce237dfd5343a61a83c8f (patch) | |
| tree | ea8b115ce4511c2e4be40b1bfa7936cf16c53506 | |
| parent | 19a2756e08ace957e4e9139117408d99290f1da3 (diff) | |
arm: tegra: patch for lp0
Add delay after switching the clock source for sclk
Change-Id: Iaca062fe4d400ace942f9d586b86e2b9e88c0ce7
Reviewed-on: http://git-master/r/48603
Reviewed-by: Ryan Wong <ryanw@nvidia.com>
Tested-by: Ryan Wong <ryanw@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_save.S | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra3_save.S b/arch/arm/mach-tegra/tegra3_save.S index 26c35f03c8df..a5e5aabcc8a0 100644 --- a/arch/arm/mach-tegra/tegra3_save.S +++ b/arch/arm/mach-tegra/tegra3_save.S @@ -571,10 +571,11 @@ powerdown_l2_done: ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] orr r0, r0, #MSELECT_CLKM str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] + ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] - /* 2 us delay between changing sclk and disabling PLLs */ + /* 5 us delay between changing sclk and disabling PLLs */ wait_for_us r1, r7, r9 - add r1, r1, #2 + add r1, r1, #5 wait_until r1, r7, r9 /* switch to CLKS */ |