video: tegra: dc: fix tiled memory efficiency

Tegra3 also supports LPDDR2 which has no tiled memory inefficiency as in DDR3.
This patch adds one memory controller API to retrive tiled memory efficiency.

BUG 847731

Change-Id: I407914c6035389b696040947e7aebc6ecdb92bb1
Reviewed-on: http://git-master/r/40074
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

6 files changed, 41 insertions, 15 deletions

diff --git a/arch/arm/mach-tegra/include/mach/mc.h b/arch/arm/mach-tegra/include/mach/mc.h
index c2b73bd2c8b4..576153ad08d6 100644
--- a/arch/arm/mach-tegra/include/mach/mc.h
+++ b/arch/arm/mach-tegra/include/mach/mc.h
@@ -104,4 +104,6 @@ void tegra_mc_set_priority(unsigned long client, unsigned long prio);
 	do { /* nothing for now */ } while (0)
 #endif
 
+int tegra_mc_get_tiled_memory_bandwidth_multiplier(void);
+
 #endif
diff --git a/arch/arm/mach-tegra/mc.c b/arch/arm/mach-tegra/mc.c
index 57b2f6f4e223..4f2c7dac551f 100644
--- a/arch/arm/mach-tegra/mc.c
+++ b/arch/arm/mach-tegra/mc.c
@@ -42,6 +42,31 @@ void tegra_mc_set_priority(unsigned long client, unsigned long prio)
 	spin_unlock_irqrestore(&tegra_mc_lock, flags);
 
 }
+
+int tegra_mc_get_tiled_memory_bandwidth_multiplier(void)
+{
+	return 1;
+}
+
 #else
-	/* !!!FIXME!!! IMPLEMENT ME */
+	/* !!!FIXME!!! IMPLEMENT tegra_mc_set_priority() */
+
+#include "tegra3_emc.h"
+
+/*
+ * If using T30/DDR3, the 2nd 16 bytes part of DDR3 atom is 2nd line and is
+ * discarded in tiling mode.
+ */
+int tegra_mc_get_tiled_memory_bandwidth_multiplier(void)
+{
+	int type;
+
+	type = tegra_emc_get_dram_type();
+	WARN_ONCE(type == -1, "unknown type DRAM because DVFS is disabled\n");
+
+	if (type == DRAM_TYPE_DDR3)
+		return 2;
+	else
+		return 1;
+}
 #endif
diff --git a/arch/arm/mach-tegra/tegra3_emc.c b/arch/arm/mach-tegra/tegra3_emc.c
index 3a7e64e7380b..76fd8ff0a8c9 100644
--- a/arch/arm/mach-tegra/tegra3_emc.c
+++ b/arch/arm/mach-tegra/tegra3_emc.c
@@ -193,10 +193,10 @@ static bool emc_timing_in_sync;
 static const struct tegra_emc_table *tegra_emc_table;
 static int tegra_emc_table_size;
 
-static u32 dram_type;
 static u32 dram_dev_num;
 static u32 emc_cfg_saved;
 
+static u32 dram_type = -1;
 static struct clk *emc;
 
 static struct {
@@ -878,6 +878,11 @@ void tegra_emc_timing_invalidate(void)
 	emc_timing_in_sync = false;
 }
 
+int tegra_emc_get_dram_type(void)
+{
+	return dram_type;
+}
+
 #ifdef CONFIG_DEBUG_FS
 
 static struct dentry *emc_debugfs_root;
diff --git a/arch/arm/mach-tegra/tegra3_emc.h b/arch/arm/mach-tegra/tegra3_emc.h
index 2e715498abec..df3989764de6 100644
--- a/arch/arm/mach-tegra/tegra3_emc.h
+++ b/arch/arm/mach-tegra/tegra3_emc.h
@@ -45,6 +45,8 @@ struct tegra_emc_table {
 
 void tegra_init_emc(const struct tegra_emc_table *table, int table_size);
 
+int tegra_emc_get_dram_type(void);
+
 #define EMC_INTSTATUS				0x0
 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE	(0x1 << 4)
 
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c
index f7b5e2d720a7..132ec05022ed 100644
--- a/drivers/video/tegra/dc/dc.c
+++ b/drivers/video/tegra/dc/dc.c
@@ -707,16 +707,20 @@ static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
 	struct tegra_dc_win *w)
 {
 	unsigned long ret;
+	int tiled_windows_bw_multiplier;
 
 	if (!WIN_IS_ENABLED(w))
 		return 0;
 
+	tiled_windows_bw_multiplier =
+		tegra_mc_get_tiled_memory_bandwidth_multiplier();
+
 	/* perform calculations with most significant bits of pixel clock
 	 * to prevent overflow of long. */
 	ret = (unsigned long)(dc->pixel_clk >> 16) *
 		(tegra_dc_fmt_bpp(w->fmt) / 8) *
 		(WIN_USE_V_FILTER(w) ? 2 : 1) * w->w / w->out_w *
-		(WIN_IS_TILED(w) ? TILED_WINDOWS_BW_MULTIPLIER : 1);
+		(WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
 
 /*
  * Assuming 50% (X >> 1) efficiency: i.e. if we calculate we need 70MBps, we
diff --git a/drivers/video/tegra/dc/dc_priv.h b/drivers/video/tegra/dc/dc_priv.h
index ecec2ee78c4a..ebb97d9f6b22 100644
--- a/drivers/video/tegra/dc/dc_priv.h
+++ b/drivers/video/tegra/dc/dc_priv.h
@@ -41,18 +41,6 @@
 #define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * 2)
 #endif
 
-/*
- * If using T30/DDR3, the 2nd 16 bytes part of DDR3 atom is 2nd line and is
- * discarded in tiling mode.
- */
-#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
-#define TILED_WINDOWS_BW_MULTIPLIER 1
-#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
-#define TILED_WINDOWS_BW_MULTIPLIER 2
-#else
-#warning "need to revisit memory tiling effects on DC"
-#endif
-
 struct tegra_dc;
 
 struct tegra_dc_blend {