tegra: video: dc: disp1 and overlay at 204MHz

Overlay was requesting emc 400MHz always during video playback.
Playback happens in overlay which was calculated incorrectly.
Reducing it to match accurate requirement.
Calculate overlay EMC bandwidth requirement same as DC.

Change-Id: I5816d9ca1b42cd04048ca16b3e23e6d6ea312137
Reviewed-on: http://git-master/r/42507
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

4 files changed, 29 insertions, 8 deletions

diff --git a/arch/arm/mach-tegra/board-enterprise-panel.c b/arch/arm/mach-tegra/board-enterprise-panel.c
index cfe107ed62aa..f3519ab24075 100644
--- a/arch/arm/mach-tegra/board-enterprise-panel.c
+++ b/arch/arm/mach-tegra/board-enterprise-panel.c
@@ -527,7 +527,7 @@ static struct tegra_dc_out enterprise_disp1_out = {
 static struct tegra_dc_platform_data enterprise_disp1_pdata = {
 	.flags		= TEGRA_DC_FLAG_ENABLED,
 	.default_out	= &enterprise_disp1_out,
-	.emc_clk_rate	= 300000000,
+	.emc_clk_rate	= 204000000,
 	.fb		= &enterprise_dsi_fb_data,
 };
 static struct nvhost_device enterprise_disp1_device = {
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c
index 67edab4dcb3f..f7b5e2d720a7 100644
--- a/drivers/video/tegra/dc/dc.c
+++ b/drivers/video/tegra/dc/dc.c
@@ -733,19 +733,22 @@ static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
 	return ret << 16; /* restore the scaling we did above */
 }
 
-static unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[],
-	int n)
+unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
 {
 	int i;
 	struct tegra_dc *dc;
 
+	if (windows[0] == NULL)
+		return tegra_dc_get_default_emc_clk_rate(dc);
+
 	dc = windows[0]->dc;
 	BUG_ON(n > DC_N_WINDOWS);
 	/* emc rate and latency allowance both need to know per window
 	 * bandwidths */
 	for (i = 0; i < n; i++) {
 		struct tegra_dc_win *w = windows[i];
-		w->new_bandwidth = tegra_dc_calc_win_bandwidth(dc, w);
+		if (w)
+			w->new_bandwidth = tegra_dc_calc_win_bandwidth(dc, w);
 	}
 
 	return tegra_dc_find_max_bandwidth(windows, n);
diff --git a/drivers/video/tegra/dc/dc_priv.h b/drivers/video/tegra/dc/dc_priv.h
index 576396f207bf..ecec2ee78c4a 100644
--- a/drivers/video/tegra/dc/dc_priv.h
+++ b/drivers/video/tegra/dc/dc_priv.h
@@ -205,6 +205,9 @@ void tegra_dc_create_sysfs(struct device *dev);
 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable);
 bool tegra_dc_stats_get(struct tegra_dc *dc);
 
+/* defined in dc.c, used by overlay.c */
+unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *wins[], int n);
+
 /* defined in dc.c, used by dc_sysfs.c */
 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc);
 void tegra_dc_enable_crc(struct tegra_dc *dc);
diff --git a/drivers/video/tegra/dc/overlay.c b/drivers/video/tegra/dc/overlay.c
index d4bdea924612..1db1cb469b92 100644
--- a/drivers/video/tegra/dc/overlay.c
+++ b/drivers/video/tegra/dc/overlay.c
@@ -402,16 +402,31 @@ surf_err:
 	mutex_unlock(&tegra_flip_lock);
 	return err;
 }
+
 static void tegra_overlay_set_emc_freq(struct tegra_overlay_info *dev)
 {
 	unsigned long emc_freq = 0;
 	int i;
+	struct tegra_dc_win *win;
+	struct tegra_dc_win *wins[DC_N_WINDOWS];
 
-	for (i = 0; i < dev->dc->n_windows; i++) {
-		if (dev->overlays[i].owner != NULL)
-			emc_freq += dev->dc->mode.pclk*(i==1?2:1) *
-					CONFIG_TEGRA_EMC_TO_DDR_CLOCK;
+	for (i = 0; i < DC_N_WINDOWS; i++) {
+		win = tegra_dc_get_window(dev->dc, i);
+		wins[i] = win;
 	}
+
+	emc_freq = tegra_dc_get_bandwidth(wins, dev->dc->n_windows);
+
+	if (emc_freq  > tegra_dc_get_default_emc_clk_rate(dev->dc)) {
+		WARN_ONCE(emc_freq > tegra_dc_get_default_emc_clk_rate(dev->dc),
+				"Overlay: calculated EMC bandwidth is %luHz greater "
+				"than maximum allowed %luHz. Setting to max.\n",
+				emc_freq,
+				tegra_dc_get_default_emc_clk_rate(dev->dc));
+
+		emc_freq = tegra_dc_get_default_emc_clk_rate(dev->dc);
+	}
+
 	clk_set_rate(dev->dc->emc_clk, emc_freq);
 }