diff options
| author | Kevin Huang <kevinh@nvidia.com> | 2011-07-12 12:33:36 -0700 |
|---|---|---|
| committer | Ryan Wong <ryanw@nvidia.com> | 2011-07-28 17:44:41 -0700 |
| commit | 188c1125a7490d5853335e2570cc3eb641623f25 (patch) | |
| tree | 7777148a5dcc2a1e9ff36ff7c70243bb16d50615 | |
| parent | b3d30abe2f6116871edff242011b5f792c33d2f7 (diff) | |
video:tegra:dsi Add dsi one-shot mode support DO NOT MERGE
Add support for DSI one-shot mode in dsi driver.
Change-Id: Ie6762e1a0ea7c32e9a4c3a4642205da639386402
Reviewed-on: http://git-master/r/43808
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Ryan Wong <ryanw@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/dc.h | 3 | ||||
| -rw-r--r-- | drivers/video/tegra/dc/dc.c | 3 | ||||
| -rw-r--r-- | drivers/video/tegra/dc/dsi.c | 37 |
3 files changed, 27 insertions, 16 deletions
diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h index 54d34442674d..15b1b42cf3ea 100644 --- a/arch/arm/mach-tegra/include/mach/dc.h +++ b/arch/arm/mach-tegra/include/mach/dc.h @@ -154,6 +154,7 @@ struct tegra_dsi_out { bool no_pkt_seq_eot; /* 1st generation panel may not * support eot. Don't set it for * most panels. */ + bool te_polarity_low; u32 max_panel_freq_khz; u32 lp_cmd_mode_freq_khz; @@ -334,6 +335,8 @@ struct tegra_dc_out { #define TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON (0 << 2) #define TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND (1 << 2) #define TEGRA_DC_OUT_NVHDCP_POLICY_MASK (1 << 2) +#define TEGRA_DC_OUT_CONTINUOUS_MODE (0 << 3) +#define TEGRA_DC_OUT_ONE_SHOT_MODE (1 << 3) #define TEGRA_DC_ALIGN_MSB 0 #define TEGRA_DC_ALIGN_LSB 1 diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c index 973be578297b..7ccf53516ced 100644 --- a/drivers/video/tegra/dc/dc.c +++ b/drivers/video/tegra/dc/dc.c @@ -980,6 +980,9 @@ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n) tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL); + if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) + tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL); + mutex_unlock(&dc->lock); return 0; diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c index dedbd7d55f81..66281a39f419 100644 --- a/drivers/video/tegra/dc/dsi.c +++ b/drivers/video/tegra/dc/dsi.c @@ -857,30 +857,35 @@ static void tegra_dsi_start_dc_stream(struct tegra_dc *dc, tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS); /* TODO: clean up */ - val = PIN_INPUT_LSPI_INPUT_EN; - tegra_dc_writel(dc, val, DC_COM_PIN_INPUT_ENABLE3); - - val = PIN_OUTPUT_LSPI_OUTPUT_DIS; - tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3); - tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE, DC_CMD_DISPLAY_POWER_CONTROL); - val = MSF_POLARITY_HIGH | MSF_ENABLE | MSF_LSPI; - tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0); + /* Configure one-shot mode or continuous mode */ + if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) { + /* disable LSPI/LCD_DE output */ + val = PIN_OUTPUT_LSPI_OUTPUT_DIS; + tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3); + /* enable MSF & set MSF polarity */ + val = MSF_ENABLE | MSF_LSPI; + if (!dsi->info.te_polarity_low) + val |= MSF_POLARITY_HIGH; + else + val |= MSF_POLARITY_LOW; + tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0); - /* TODO: using continuous video mode for now */ - /* if (dsi->info.panel_has_frame_buffer) {*/ - if (0) { - tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY, DC_CMD_DISPLAY_COMMAND); + /* set non-continuous mode */ + tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY, + DC_CMD_DISPLAY_COMMAND); tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL); - val = GENERAL_ACT_REQ | NC_HOST_TRIG; - tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL); + tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG, + DC_CMD_STATE_CONTROL); } else { - tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND); - tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); + /* set continuous mode */ + tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, + DC_CMD_DISPLAY_COMMAND); + tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL); tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); } |