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authorPavan Kunapuli <pkunapuli@nvidia.com>2011-07-22 18:55:38 +0530
committerVarun Colbert <vcolbert@nvidia.com>2011-07-25 18:45:33 -0700
commit1279d2144aedbf821c964d8cb8dae264a0144f71 (patch)
treeb7af361b3f7a257573237d0cff81319bd051e269
parent6e615924c9641c1f733e5b636b732235f46dbbef (diff)
ARM: Tegra: Cardhu: Adding SDMMC drive strengths
Configuring the drive strengths for SDMMC1, SDMMC3 and SDMMC4. Bug 799568 Bug 826694 Change-Id: Ib18c002993eddaf622f48faa0b4e4c9deb0f8e3c Reviewed-on: http://git-master/r/42608 Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/board-cardhu-pinmux.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-pinmux.c b/arch/arm/mach-tegra/board-cardhu-pinmux.c
index 1fcafe17ddc1..779876e8318d 100644
--- a/arch/arm/mach-tegra/board-cardhu-pinmux.c
+++ b/arch/arm/mach-tegra/board-cardhu-pinmux.c
@@ -85,6 +85,19 @@ static __initdata struct tegra_drive_pingroup_config cardhu_drive_pinmux[] = {
/* UART3 */
SET_DRIVE(UART3, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+ /* SDMMC1 */
+ SET_DRIVE(SDIO1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+ /* SDMMC3 */
+ SET_DRIVE(SDIO3, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+ /* SDMMC4 */
+ SET_DRIVE(GMA, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+ SET_DRIVE(GMB, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+ SET_DRIVE(GMC, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+ SET_DRIVE(GMD, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
};
#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io) \