diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-07-13 18:55:44 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-07-15 16:09:48 -0700 |
| commit | 3239dc690305147fc7d368eca44b5b47553969f5 (patch) | |
| tree | ace1f49e01fb9c9765290db6e2aed60ec336be30 | |
| parent | 614180886aee985f0a2f1ca31d500ecd7d490d5c (diff) | |
ARM: tegra: clock: Update EMC parents after deep sleep
On Tegra3 EMC parents may be changed underneath clock framework by low
level resume code. Updated parents ref-count respectively in such case.
Change-Id: Ib3fbe4915c5f5a24dcf1686f060e9bc1144c8559
Reviewed-on: http://git-master/r/40959
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index c20b66fb354a..807e9b32e08e 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -4323,6 +4323,7 @@ void tegra_clk_resume(void) u32 plla_base; u32 plld_base; u32 plld2_base; + struct clk *p; val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK; val |= *ctx++; @@ -4421,9 +4422,22 @@ void tegra_clk_resume(void) clk_writel(plld_base, tegra_pll_d.reg + PLL_BASE); clk_writel(plld2_base, tegra_pll_d2.reg + PLL_BASE); - /* Since EMC clock is not restored update current state, and mark - EMC DFS as out of sync */ + /* Since EMC clock is not restored, and may not preserve parent across + suspend, update current state, and mark EMC DFS as out of sync */ + p = tegra_clk_emc.parent; tegra3_periph_clk_init(&tegra_clk_emc); + + if (p != tegra_clk_emc.parent) { + /* FIXME: old parent is left enabled here even if EMC was its + only child before suspend (never happens on Tegra3) */ + pr_debug("EMC parent(refcount) across suspend: %s(%d) : %s(%d)", + p->name, p->refcnt, tegra_clk_emc.parent->name, + tegra_clk_emc.parent->refcnt); + + BUG_ON(!p->refcnt); + p->refcnt--; + tegra_clk_emc.parent->refcnt++; + } tegra_emc_timing_invalidate(); tegra3_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */ |