diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-06-11 22:11:18 -0700 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-06-14 16:11:08 -0700 |
| commit | e35e75d259df38f9308f9b02619b8d61b180dbe0 (patch) | |
| tree | f71129a70be4caba51a0a4ed30bba9da7676e4ac | |
| parent | 4d80138afa36b758f3737eac3e48aaf695569982 (diff) | |
Revert "usb: fsl_udc: tegra: Fix for reducing turnaround errors."
This reverts commit 141f664e2b5052d7fcd57c5287ae1e27db0f658b.
The original commit
(a) renamed con_id for shared user clock from "sclk" to "hclk"
(b) increased requested clock rate
Since there is no "hclk" shared bus in tegra clock tree, this
effectively disabled busy hint from USB driver, and actually
reduced the bus clock (instead of increasing it).
Bug 821986 sated that clock effect has not been tested.
Reverting it would at least restore 80MHz bus clock limit required
for USB operations.
Change-Id: I280340699df96c1cd21e3d8c0a65b5f89a7607b4
Reviewed-on: http://git-master/r/36200
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
| -rw-r--r-- | drivers/usb/gadget/fsl_tegra_udc.c | 36 |
1 files changed, 15 insertions, 21 deletions
diff --git a/drivers/usb/gadget/fsl_tegra_udc.c b/drivers/usb/gadget/fsl_tegra_udc.c index d8b1e1700894..850825a89d01 100644 --- a/drivers/usb/gadget/fsl_tegra_udc.c +++ b/drivers/usb/gadget/fsl_tegra_udc.c @@ -16,7 +16,7 @@ static struct tegra_usb_phy *phy; static struct clk *udc_clk; static struct clk *emc_clk; -static struct clk *hclk_clk; +static struct clk *sclk_clk; static void *udc_base; int fsl_udc_clk_init(struct platform_device *pdev) @@ -35,21 +35,15 @@ int fsl_udc_clk_init(struct platform_device *pdev) clk_enable(udc_clk); - hclk_clk = clk_get(&pdev->dev, "hclk"); - if (IS_ERR(hclk_clk)) { - dev_err(&pdev->dev, "Can't get hclk clock\n"); - err = PTR_ERR(hclk_clk); - goto err_hclk; + sclk_clk = clk_get(&pdev->dev, "sclk"); + if (IS_ERR(sclk_clk)) { + dev_err(&pdev->dev, "Can't get sclk clock\n"); + err = PTR_ERR(sclk_clk); + goto err_sclk; } -#ifdef CONFIG_ARCH_TEGRA_2x_SOC - /* Set hclk to 240MHz. For Tegra 2x SOC */ - clk_set_rate(hclk_clk, 240000000); -#else - /* Set hclk to 216MHz. For Tegra 3x SOC */ - clk_set_rate(hclk_clk, 216000000); -#endif - clk_enable(hclk_clk); + clk_set_rate(sclk_clk, 80000000); + clk_enable(sclk_clk); emc_clk = clk_get(&pdev->dev, "emc"); if (IS_ERR(emc_clk)) { @@ -101,9 +95,9 @@ err0: clk_disable(emc_clk); clk_put(emc_clk); err_emc: - clk_disable(hclk_clk); - clk_put(hclk_clk); -err_hclk: + clk_disable(sclk_clk); + clk_put(sclk_clk); +err_sclk: clk_disable(udc_clk); clk_put(udc_clk); return err; @@ -122,8 +116,8 @@ void fsl_udc_clk_release(void) clk_disable(udc_clk); clk_put(udc_clk); - clk_disable(hclk_clk); - clk_put(hclk_clk); + clk_disable(sclk_clk); + clk_put(sclk_clk); clk_disable(emc_clk); clk_put(emc_clk); @@ -133,14 +127,14 @@ void fsl_udc_clk_suspend(bool is_dpd) { tegra_usb_phy_power_off(phy, is_dpd); clk_disable(udc_clk); - clk_disable(hclk_clk); + clk_disable(sclk_clk); clk_disable(emc_clk); } void fsl_udc_clk_resume(bool is_dpd) { clk_enable(emc_clk); - clk_enable(hclk_clk); + clk_enable(sclk_clk); clk_enable(udc_clk); tegra_usb_phy_power_on(phy, is_dpd); } |