diff options
| author | Luke Huang <lhuang@nvidia.com> | 2011-06-06 13:05:44 -0700 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-06-14 16:09:40 -0700 |
| commit | b72cba2358e12a2374e838add5b862aa08cfe4dc (patch) | |
| tree | 71e2d2a77a7aedff8a8951804f8ed66cf8695343 | |
| parent | 03e9e008d1ee12afee36f717923677fa64c4b700 (diff) | |
arm: tegra: power: fix lp0 resume failure
Do not check PLLX lock bit on PLLX sanity check, since it might not be in the
lock state yet.
Change-Id: I607210330dc355a1359dc856a192bd4163df4cb3
Reviewed-on: http://git-master/r/35261
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/suspend.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/suspend.c b/arch/arm/mach-tegra/suspend.c index 9dd880fb02ae..d87ce541f31e 100644 --- a/arch/arm/mach-tegra/suspend.c +++ b/arch/arm/mach-tegra/suspend.c @@ -376,8 +376,10 @@ static noinline void restore_cpu_complex(void) * by CPU boot-up code - wait for PLL stabilization if PLLX * was enabled */ - BUG_ON(readl(clk_rst + CLK_RESET_PLLX_BASE) != - tegra_sctx.pllx_base); + reg = readl(clk_rst + CLK_RESET_PLLX_BASE); + /* mask out bit 27 - not to check PLL lock bit */ + BUG_ON((reg & (~(1 << 27))) != + (tegra_sctx.pllx_base & (~(1 << 27)))); if (tegra_sctx.pllx_base & (1<<30)) { #if USE_PLL_LOCK_BITS |