ARM: tegra: dvfs: Update DVFS tables with data for T30S

Change-Id: I38b9752adc9e927935fe7ffe5590c41577a45809
Reviewed-on: http://git-master/r/34381
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

5 files changed, 57 insertions, 43 deletions

diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h
index 50fe81416f9f..44d09225667f 100644
--- a/arch/arm/mach-tegra/dvfs.h
+++ b/arch/arm/mach-tegra/dvfs.h
@@ -21,7 +21,7 @@
 #ifndef _TEGRA_DVFS_H_
 #define _TEGRA_DVFS_H_
 
-#define MAX_DVFS_FREQS	16
+#define MAX_DVFS_FREQS	18
 
 struct clk;
 struct dvfs_rail;
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index eb2ba152c526..0ad5cef7a40e 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -99,11 +99,9 @@ void tegra_init_fuse(void)
 	writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
 	tegra_init_speedo_data();
 
-	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d "
-		"Speedo ID: %d\n",
-		tegra_get_revision_name(),
-		tegra_sku_id(), tegra_cpu_process_id(),
-		tegra_core_process_id(), tegra_soc_speedo_id());
+	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
+		tegra_get_revision_name(), tegra_sku_id(),
+		tegra_cpu_process_id(), tegra_core_process_id());
 }
 
 unsigned long long tegra_chip_uid(void)
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index ee383f669e71..48ee9bf1ac7b 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -51,6 +51,7 @@ const char *tegra_get_revision_name(void);
 
 int tegra_cpu_process_id(void);
 int tegra_core_process_id(void);
+int tegra_cpu_speedo_id(void);
 int tegra_soc_speedo_id(void);
 void tegra_init_speedo_data(void);
 
@@ -58,6 +59,7 @@ void tegra_init_speedo_data(void);
 
 static inline int tegra_cpu_process_id(void) { return 0; }
 static inline int tegra_core_process_id(void) { return 0; }
+static inline int tegra_cpu_speedo_id(void) { return 0; }
 static inline int tegra_soc_speedo_id(void) { return 0; }
 static inline void tegra_init_speedo_data(void) { }
 
diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
index 42d8069e7f41..6bfffcc54b72 100644
--- a/arch/arm/mach-tegra/tegra3_dvfs.c
+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
@@ -28,7 +28,7 @@ static bool tegra_dvfs_cpu_disabled;
 static bool tegra_dvfs_core_disabled;
 
 static const int cpu_millivolts[MAX_DVFS_FREQS] =
-	{750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125};
+	{750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125, 1150};
 
 static const int core_millivolts[MAX_DVFS_FREQS] =
 	{1000, 1050, 1100, 1150, 1200, 1250, 1300};
@@ -38,8 +38,8 @@ static const int core_speedo_nominal_millivolts[] =
 	{ 1200, 1200, 1300 };
 
 static const int cpu_speedo_nominal_millivolts[] =
-/* speedo_id 0,    1,    2 */
-	{ 1125, 1125, 1125 };
+/* speedo_id 0,    1,    2,    3 */
+	{ 1125, 1150, 1125, 1150 };
 
 #define KHZ 1000
 #define MHZ 1000000
@@ -48,8 +48,8 @@ static const int cpu_speedo_nominal_millivolts[] =
 
 static struct dvfs_rail tegra3_dvfs_rail_vdd_cpu = {
 	.reg_id = "vdd_cpu",
-	.max_millivolts = 1125,
-	.min_millivolts = 800,
+	.max_millivolts = 1150,
+	.min_millivolts = 750,
 	.step = VDD_CPU_BELOW_VDD_CORE_MAX,
 };
 
@@ -110,21 +110,25 @@ static struct dvfs_relationship tegra3_dvfs_relationships[] = {
 	}
 
 static struct dvfs cpu_dvfs_table[] = {
-	/* Cpu voltages (mV):	     750, 775, 800, 825, 850, 875,  900,  925,  950,  975, 1000, 1025, 1050, 1075, 1100, 1125 */
+	/* Cpu voltages (mV):	     750, 775, 800, 825, 850, 875,  900,  925,  950,  975, 1000, 1025, 1050, 1075, 1100, 1125, 1150*/
 	CPU_DVFS("cpu_g", 0, 0, MHZ, 399, 399, 541, 541, 684, 684,  817,  817,  817, 1026, 1102, 1149, 1187, 1225, 1282, 1300),
 	CPU_DVFS("cpu_g", 0, 1, MHZ, 481, 481, 652, 652, 807, 807,  948,  948,  948, 1117, 1171, 1206, 1300),
 	CPU_DVFS("cpu_g", 0, 2, MHZ, 540, 540, 711, 711, 883, 883, 1039, 1039, 1039, 1178, 1206, 1300),
 	CPU_DVFS("cpu_g", 0, 3, MHZ, 570, 570, 777, 777, 931, 931, 1102, 1102, 1102, 1216, 1300),
 
-	CPU_DVFS("cpu_g", 1, 0, MHZ, 399, 399, 541, 541, 684, 684,  817,  817,  817, 1026, 1102, 1149, 1187, 1225, 1282, 1300),
-	CPU_DVFS("cpu_g", 1, 1, MHZ, 481, 481, 652, 652, 807, 807,  948,  948,  948, 1117, 1171, 1206, 1300),
-	CPU_DVFS("cpu_g", 1, 2, MHZ, 540, 540, 711, 711, 883, 883, 1039, 1039, 1039, 1178, 1206, 1300),
-	CPU_DVFS("cpu_g", 1, 3, MHZ, 570, 570, 777, 777, 931, 931, 1102, 1102, 1102, 1216, 1300),
+	CPU_DVFS("cpu_g", 1, 0, MHZ,   1, 399, 399, 541, 541, 684,  684,  817,  817,  817, 1026, 1102, 1149, 1187, 1225, 1282, 1300),
+	CPU_DVFS("cpu_g", 1, 1, MHZ,   1, 481, 481, 652, 652, 807,  807,  948,  948,  948, 1117, 1171, 1206, 1300),
+	CPU_DVFS("cpu_g", 1, 2, MHZ,   1, 540, 540, 711, 711, 883,  883, 1039, 1039, 1039, 1178, 1206, 1300),
+	CPU_DVFS("cpu_g", 1, 3, MHZ,   1, 570, 570, 777, 777, 931,  931, 1102, 1102, 1102, 1216, 1300),
 
 	CPU_DVFS("cpu_g", 2, 1, MHZ, 481, 481, 652, 652, 807, 807,  948,  948,  948, 1117, 1171, 1206, 1254, 1292, 1311, 1400),
 	CPU_DVFS("cpu_g", 2, 2, MHZ, 540, 540, 711, 711, 883, 883, 1039, 1039, 1039, 1178, 1206, 1263, 1301, 1400),
 	CPU_DVFS("cpu_g", 2, 3, MHZ, 570, 570, 777, 777, 931, 931, 1102, 1102, 1102, 1216, 1255, 1304, 1400),
 
+	CPU_DVFS("cpu_g", 3, 1, MHZ,   1, 481, 481, 652, 652, 807,  807,  948,  948,  948, 1117, 1171, 1206, 1254, 1292, 1311, 1400),
+	CPU_DVFS("cpu_g", 3, 2, MHZ,   1, 540, 540, 711, 711, 883,  883, 1039, 1039, 1039, 1178, 1206, 1263, 1301, 1400),
+	CPU_DVFS("cpu_g", 3, 3, MHZ,   1, 570, 570, 777, 777, 931,  931, 1102, 1102, 1102, 1216, 1255, 1304, 1400),
+
 	/*
 	 * "Safe entry" to be used when no match for chip speedo, process
 	 *  corner is found (just to boot at low rate); must be the last one
@@ -402,7 +406,8 @@ static int __init get_core_nominal_mv_index(int speedo_id)
 
 void __init tegra_soc_init_dvfs(void)
 {
-	int speedo_id = tegra_soc_speedo_id();
+	int cpu_speedo_id = tegra_cpu_speedo_id();
+	int soc_speedo_id = tegra_soc_speedo_id();
 	int cpu_process_id = tegra_cpu_process_id();
 	int core_process_id = tegra_core_process_id();
 
@@ -422,7 +427,7 @@ void __init tegra_soc_init_dvfs(void)
 	 * init. Nominal voltage index in the scaling ladder will also be
 	 * used to determine max dvfs frequency for the respective domains.
 	 */
-	core_nominal_mv_index = get_core_nominal_mv_index(speedo_id);
+	core_nominal_mv_index = get_core_nominal_mv_index(soc_speedo_id);
 	if (core_nominal_mv_index < 0) {
 		tegra3_dvfs_rail_vdd_core.disabled = true;
 		tegra_dvfs_core_disabled = true;
@@ -432,7 +437,7 @@ void __init tegra_soc_init_dvfs(void)
 		core_millivolts[core_nominal_mv_index];
 
 	cpu_nominal_mv_index = get_cpu_nominal_mv_index(
-		speedo_id, cpu_process_id, &cpu_dvfs);
+		cpu_speedo_id, cpu_process_id, &cpu_dvfs);
 	BUG_ON((cpu_nominal_mv_index < 0) || (!cpu_dvfs));
 	tegra3_dvfs_rail_vdd_cpu.nominal_millivolts =
 		cpu_millivolts[cpu_nominal_mv_index];
@@ -446,7 +451,7 @@ void __init tegra_soc_init_dvfs(void)
 	   initialize dvfs-ed clocks */
 	for (i = 0; i <  ARRAY_SIZE(core_dvfs_table); i++) {
 		struct dvfs *d = &core_dvfs_table[i];
-		if (!match_dvfs_one(d, speedo_id, core_process_id))
+		if (!match_dvfs_one(d, soc_speedo_id, core_process_id))
 			continue;
 		init_dvfs_one(d, core_nominal_mv_index);
 	}
diff --git a/arch/arm/mach-tegra/tegra3_speedo.c b/arch/arm/mach-tegra/tegra3_speedo.c
index 9b19516db61b..9560c7f0acf5 100644
--- a/arch/arm/mach-tegra/tegra3_speedo.c
+++ b/arch/arm/mach-tegra/tegra3_speedo.c
@@ -41,13 +41,15 @@ static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = {
 /* Maximum speedo levels for each CPU process corner */
 static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
 /* proc_id 0    1    2    3 */
-	{306, 338, 360, 376}, /* soc_speedo_id 0 */
-	{306, 338, 360, 376}, /* soc_speedo_id 1 */
-	{338, 338, 360, 376}, /* soc_speedo_id 2 */
+	{306, 338, 360, 376}, /* cpu_speedo_id 0 */
+	{306, 338, 360, 376}, /* cpu_speedo_id 1 */
+	{338, 338, 360, 376}, /* cpu_speedo_id 2 */
+	{338, 338, 360, 376}, /* cpu_speedo_id 3 */
 };
 
 static int cpu_process_id;
 static int core_process_id;
+static int cpu_speedo_id;
 static int soc_speedo_id;
 
 static inline u8 fuse_package_info(void)
@@ -70,48 +72,53 @@ static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
 	*speedo_g = ((reg >> 16) & 0xFFFF) * 4;
 }
 
-static int rev_sku_to_soc_speedo(int rev, int sku)
+static void rev_sku_to_speedo_ids(int rev, int sku)
 {
-	int soc_speedo;
 	u8 pkg;
 
 	switch (rev) {
 	case TEGRA_REVISION_A01:
-		pr_warning("Tegra3 Rev-A01: Using default Speedo: 0\n");
-		soc_speedo = 0;
+		cpu_speedo_id = 0;
+		soc_speedo_id = 0;
 		break;
 	case TEGRA_REVISION_A02:
 		switch (sku) {
 		case 0x87: /* AP30 */
-			soc_speedo = 1;
+			cpu_speedo_id = 1;
+			soc_speedo_id = 1;
 			break;
 		case 0x81: /* T30 */
-			soc_speedo = 2;
+			cpu_speedo_id = 2;
+			soc_speedo_id = 2;
 			break;
 		case 0x83: /* T30S */
-			soc_speedo = 0; /* FIXME => 3 when table avbl */
+			cpu_speedo_id = 3;
+			soc_speedo_id = 2;
 			break;
 		case 0:    /* ENG - check PKG_SKU */
 			pr_info("Tegra3 ENG SKU: Checking pkg info\n");
 			pkg = fuse_package_info();
 			switch (pkg) {
 			case 1: /* MID => assume T30 */
-				soc_speedo = 2;
+				cpu_speedo_id = 2;
+				soc_speedo_id = 2;
 				break;
 			case 2: /* DSC => assume T30S */
-				soc_speedo = 0; /* FIXME => 3 when table avbl */
+				cpu_speedo_id = 3;
+				soc_speedo_id = 2;
 				break;
 			default:
 				pr_err("Tegra3 Rev-A02: Reserved pkg info %d\n",
 				       pkg);
-				soc_speedo = 0;
+				BUG();
 				break;
 			}
 			break;
 		default:
 			/* FIXME: replace with BUG() when all SKU's valid */
 			pr_err("Tegra3 Rev-A02: Unknown SKU %d\n", sku);
-			soc_speedo = 0;
+			cpu_speedo_id = 0;
+			soc_speedo_id = 0;
 			break;
 		}
 		break;
@@ -119,10 +126,6 @@ static int rev_sku_to_soc_speedo(int rev, int sku)
 		BUG();
 		break;
 	}
-
-	pr_debug("Tegra3 Package: %d SKU: %d Rev: %s Speedo: %d",
-		 pkg, sku, tegra_get_revision_name(), soc_speedo);
-	return soc_speedo;
 }
 
 void tegra_init_speedo_data(void)
@@ -130,16 +133,16 @@ void tegra_init_speedo_data(void)
 	u32 cpu_speedo_val, core_speedo_val;
 	int iv;
 
-	soc_speedo_id = rev_sku_to_soc_speedo(tegra_get_revision(),
-					      tegra_sku_id());
-	BUG_ON(soc_speedo_id >= ARRAY_SIZE(cpu_process_speedos));
+	rev_sku_to_speedo_ids(tegra_get_revision(), tegra_sku_id());
+	BUG_ON(cpu_speedo_id >= ARRAY_SIZE(cpu_process_speedos));
+	BUG_ON(soc_speedo_id >= ARRAY_SIZE(core_process_speedos));
 
 	fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
 	pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val);
 	pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val);
 
 	for (iv = 0; iv < PROCESS_CORNERS_NUM; iv++) {
-		if (cpu_speedo_val < cpu_process_speedos[soc_speedo_id][iv]) {
+		if (cpu_speedo_val < cpu_process_speedos[cpu_speedo_id][iv]) {
 			break;
 		}
 	}
@@ -176,7 +179,8 @@ void tegra_init_speedo_data(void)
 		soc_speedo_id = 0;
 	}
 
-	pr_debug("%s Soc speedo value %d", __func__, soc_speedo_id);
+	pr_info("Tegra3: CPU Speedo ID %d, Soc Speedo ID %d",
+		 cpu_speedo_id, soc_speedo_id);
 }
 
 int tegra_cpu_process_id(void)
@@ -197,6 +201,11 @@ int tegra_core_process_id(void)
 		return core_process_id;
 }
 
+int tegra_cpu_speedo_id(void)
+{
+	return cpu_speedo_id;
+}
+
 int tegra_soc_speedo_id(void)
 {
 	return soc_speedo_id;