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authorLaxman Dewangan <ldewangan@nvidia.com>2011-06-08 23:38:55 +0530
committerNiket Sirsi <nsirsi@nvidia.com>2011-06-14 16:10:17 -0700
commit63922cce38ddf2f57cc1ddc2c577f873251ab8d4 (patch)
tree06a256c24cd918c93d4d059535c4a48d0b5a97be
parent5c94c0c364d75c9b747a7c1d7e4e9e9521fb7c09 (diff)
arm: tegra: cardhu: Changes for E1291-A04 power rails
The E1291-A04 power rails are different then the A02/A03 version of E1291. Supporting the A04 power rails properly. Change-Id: I4c7dc0afa5b6bb1a7350418ef07f4ee7192cff30 Reviewed-on: http://git-master/r/35722 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/board-cardhu-power.c47
1 files changed, 42 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-power.c b/arch/arm/mach-tegra/board-cardhu-power.c
index c85bd4cb11e6..eb5de88a114d 100644
--- a/arch/arm/mach-tegra/board-cardhu-power.c
+++ b/arch/arm/mach-tegra/board-cardhu-power.c
@@ -696,11 +696,13 @@ static int disable_load_switch_rail(
.disable_rail = _disable, \
}
-/* common to all boards */
+/* common to most of boards*/
GREG_INIT(0, en_5v_cp, en_5v_cp, NULL, TPS6591X_GPIO_GP0, false, 1, 0, 0, 0);
GREG_INIT(1, en_5v0, en_5v0, NULL, TPS6591X_GPIO_GP2, false, 0, 0, 0, 0);
GREG_INIT(2, en_ddr, en_ddr, NULL, TPS6591X_GPIO_GP6, false, 0, 0, 0, 0);
GREG_INIT(3, en_3v3_sys, en_3v3_sys, NULL, TPS6591X_GPIO_GP7, false, 0, 0, 0, 0);
+
+
GREG_INIT(4, en_vdd_bl, en_vdd_bl, NULL, TEGRA_GPIO_PK3, false, 1, 0, 0, 0);
GREG_INIT(5, en_3v3_modem, en_3v3_modem, NULL, TEGRA_GPIO_PD6, false, 1, 0, 0, 0);
GREG_INIT(6, en_vdd_pnl1, en_vdd_pnl1, "vdd_3v3_devices", TEGRA_GPIO_PL4, false, 1, 0, 0, 0);
@@ -712,6 +714,12 @@ GREG_INIT(11, en_vdd_sdmmc1, en_vdd_sdmmc1, "vdd_3v3_devices", TEGRA_GPIO_PD7,
GREG_INIT(12, en_3v3_pex_hvdd, en_3v3_pex_hvdd, "vdd_3v3_devices", TEGRA_GPIO_PL7, false, 0, 0, 0, 0);
GREG_INIT(13, en_1v8_cam, en_1v8_cam, "vdd_gen1v8", TEGRA_GPIO_PBB4, false, 0, 0, 0, 0);
+/* E1291-A04 specific */
+GREG_INIT(1, en_5v0_a04, en_5v0, NULL, TPS6591X_GPIO_GP8, false, 0, 0, 0, 0);
+GREG_INIT(2, en_ddr_a04, en_ddr, NULL, TPS6591X_GPIO_GP7, false, 0, 0, 0, 0);
+GREG_INIT(3, en_3v3_sys_a04, en_3v3_sys, NULL, TPS6591X_GPIO_GP6, false, 0, 0, 0, 0);
+
+
/*Specific to pm269*/
GREG_INIT(4, en_vdd_bl_p269, en_vdd_bl, NULL,
TEGRA_GPIO_PH3, false, 1, 0, 0, 0);
@@ -772,6 +780,7 @@ GREG_INIT(21, en_vdd_bl2_a03, en_vdd_bl2, NULL, TEGRA_GPIO_PDD0, false, 1, 0,
GREG_INIT(22, en_vbrtr, en_vbrtr, "vdd_3v3_devices", PMU_TCA6416_GPIO_PORT12, false, 0, 0, 0, 0);
#define ADD_GPIO_REG(_name) &gpio_pdata_##_name
+
#define COMMON_GPIO_REG \
ADD_GPIO_REG(en_5v_cp), \
ADD_GPIO_REG(en_5v0), \
@@ -787,6 +796,21 @@ GREG_INIT(22, en_vbrtr, en_vbrtr, "vdd_3v3_devices", PMU_TCA6416_GPIO_PORT12, f
ADD_GPIO_REG(en_3v3_pex_hvdd), \
ADD_GPIO_REG(en_1v8_cam),
+#define COMMON_GPIO_REG_E1291_A04 \
+ ADD_GPIO_REG(en_5v_cp), \
+ ADD_GPIO_REG(en_5v0_a04), \
+ ADD_GPIO_REG(en_ddr_a04), \
+ ADD_GPIO_REG(en_3v3_sys_a04), \
+ ADD_GPIO_REG(en_3v3_modem), \
+ ADD_GPIO_REG(en_vdd_pnl1), \
+ ADD_GPIO_REG(cam3_ldo_en), \
+ ADD_GPIO_REG(en_vdd_com), \
+ ADD_GPIO_REG(en_3v3_fuse), \
+ ADD_GPIO_REG(en_3v3_emmc), \
+ ADD_GPIO_REG(en_vdd_sdmmc1), \
+ ADD_GPIO_REG(en_3v3_pex_hvdd), \
+ ADD_GPIO_REG(en_1v8_cam),
+
#define PM269_GPIO_REG \
ADD_GPIO_REG(en_5v_cp), \
ADD_GPIO_REG(en_5v0), \
@@ -858,6 +882,14 @@ static struct gpio_switch_regulator_subdev_data *gswitch_subdevs_e1291_a03[] = {
E1198_GPIO_REG
};
+/* Gpio switch regulator platform data for E1291 A04*/
+static struct gpio_switch_regulator_subdev_data *gswitch_subdevs_e1291_a04[] = {
+ COMMON_GPIO_REG_E1291_A04
+ E1291_A03_GPIO_REG
+ E1198_GPIO_REG
+};
+
+
static struct gpio_switch_regulator_platform_data gswitch_pdata;
static struct platform_device gswitch_regulator_pdata = {
.name = "gpio-switch-regulator",
@@ -878,14 +910,19 @@ int __init cardhu_gpio_switch_regulator_init(void)
gswitch_pdata.subdevs = gswitch_subdevs_e1198;
break;
case BOARD_E1291:
- if (board_info.fab >= 0x3) {
+ if (board_info.fab == 0x3) {
gswitch_pdata.num_subdevs =
ARRAY_SIZE(gswitch_subdevs_e1291_a03);
gswitch_pdata.subdevs = gswitch_subdevs_e1291_a03;
- break;
+ } else if (board_info.fab == 0x4) {
+ gswitch_pdata.num_subdevs =
+ ARRAY_SIZE(gswitch_subdevs_e1291_a04);
+ gswitch_pdata.subdevs = gswitch_subdevs_e1291_a04;
+ } else {
+ gswitch_pdata.num_subdevs =
+ ARRAY_SIZE(gswitch_subdevs_e1198);
+ gswitch_pdata.subdevs = gswitch_subdevs_e1198;
}
- gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_e1198);
- gswitch_pdata.subdevs = gswitch_subdevs_e1198;
break;
case BOARD_PM269:
gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_pm269);