diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-06-10 12:58:11 -0700 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-06-14 16:21:14 -0700 |
| commit | 164e8504b26dedea90ff025d8e973263aae0dffb (patch) | |
| tree | 1c80b9ae363cc828a2fad921a4a60df27512a6b9 | |
| parent | e7f839a1a0d2c21b459aa6b99504ac7dbf676ca0 (diff) | |
arm: tegra: clocks: Support standard PLL-P frequency for FPGAs
FPGA platforms require the standard PLL-P frequency. Configure
the clock tables approprately based upon platform type.
Change-Id: I0c39c819cc935715d19ba684d365dcf9a1f2b518
Reviewed-on: http://git-master/r/36150
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 14 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 8 |
2 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 03562f36be79..ed708270158b 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -103,6 +103,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { /* set up clocks that should always be on */ /* name parent rate enabled */ { "clk_m", NULL, 0, true }, +#ifndef CONFIG_TEGRA_FPGA_PLATFORM #ifdef CONFIG_ARCH_TEGRA_2x_SOC { "pll_p", NULL, 216000000, true }, { "pll_p_out1", "pll_p", 28800000, true }, @@ -126,6 +127,19 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "hclk", "sclk", 102000000, true }, { "pclk", "hclk", 51000000, true }, #endif +#else + { "pll_p", NULL, 216000000, true }, + { "pll_p_out1", "pll_p", 28800000, true }, + { "pll_p_out2", "pll_p", 48000000, true }, + { "pll_p_out3", "pll_p", 72000000, true }, + { "pll_m_out1", "pll_m", 275000000, true }, + { "pll_c", NULL, ULONG_MAX, false }, + { "pll_c_out1", "pll_c", 208000000, false }, + { "pll_p_out4", "pll_p", 108000000, true }, + { "sclk", "pll_p_out4", 108000000, true }, + { "hclk", "sclk", 108000000, true }, + { "pclk", "hclk", 54000000, true }, +#endif { "pll_x", NULL, 0, true }, { "cpu", NULL, 0, true }, { "emc", NULL, 0, true }, diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 546abe7fea49..820710b284cc 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -2702,7 +2702,11 @@ static struct clk tegra_pll_p = { .vco_max = 1400000000, .freq_table = tegra_pll_p_freq_table, .lock_delay = 300, +#ifndef CONFIG_TEGRA_FPGA_PLATFORM .fixed_rate = 408000000, +#else + .fixed_rate = 216000000, +#endif }, }; @@ -3303,7 +3307,11 @@ static struct clk tegra_clk_sbus_cmplx = { .hclk = &tegra_clk_hclk, .sclk_low = &tegra_pll_p_out4, .sclk_high = &tegra_pll_m_out1, +#ifndef CONFIG_TEGRA_FPGA_PLATFORM .threshold = 204000000, /* exact factor of low range pll_p */ +#else + .threshold = 108000000, /* exact factor of low range pll_p */ +#endif }, }; |