diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-11-01 19:39:15 -0700 |
|---|---|---|
| committer | Ryan Wong <ryanw@nvidia.com> | 2011-11-03 20:38:52 -0700 |
| commit | ace3c721f0a0757d0498f9f69214f322976fb6cc (patch) | |
| tree | 7987591b17b9014dd2dc872efae5a66e23918829 | |
| parent | bb84bdbfc8c16675b8bf7986ead9a410a00f1679 (diff) | |
ARM: tegra: clock: Add DSR field to Tegra3 EMC DFS table
Added dynamic self-refresh (DSR) field to Tegra3 EMC DFS table. This
field will be supported starting with table revision to 3.2, and it
will allow to enable/disable DSR for each table entry independently.
Bug 853990
Reviewed-on: http://git-master/r/#change,61702
(cherry picked from commit 0e7347fd3bb6266ce3c84f1186d60f13205c85a5)
Change-Id: I803150b71703e3e06545c87331167a976959296c
Reviewed-on: http://git-master/r/62295
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Ryan Wong <ryanw@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_emc.c | 13 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_emc.h | 1 |
2 files changed, 11 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra3_emc.c b/arch/arm/mach-tegra/tegra3_emc.c index 49833f28f56a..56d579972369 100644 --- a/arch/arm/mach-tegra/tegra3_emc.c +++ b/arch/arm/mach-tegra/tegra3_emc.c @@ -567,6 +567,8 @@ static noinline void emc_set_clock(const struct tegra_emc_table *next_timing, EMC_AUTO_CAL_INTERVAL); /* 16. restore dynamic self-refresh */ + if (next_timing->rev >= 0x32) + dyn_sref_enabled = next_timing->emc_dsr; if (dyn_sref_enabled) { emc_cfg_reg |= EMC_CFG_DYN_SREF_ENABLE; emc_writel(emc_cfg_reg, EMC_CFG); @@ -606,9 +608,13 @@ static inline void emc_get_timing(struct tegra_emc_table *timing) static inline void emc_cfg_power_restore(void) { u32 reg = emc_readl(EMC_CFG); - if ((reg ^ emc_cfg_saved) & EMC_CFG_PWR_MASK) { - reg = (reg & (~EMC_CFG_PWR_MASK)) | - (emc_cfg_saved & EMC_CFG_PWR_MASK); + u32 pwr_mask = EMC_CFG_PWR_MASK; + + if (tegra_emc_table[0].rev >= 0x32) + pwr_mask &= ~EMC_CFG_DYN_SREF_ENABLE; + + if ((reg ^ emc_cfg_saved) & pwr_mask) { + reg = (reg & (~pwr_mask)) | (emc_cfg_saved & pwr_mask); emc_writel(reg, EMC_CFG); emc_timing_update(); } @@ -845,6 +851,7 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size) emc_num_burst_regs = 105; break; case 0x31: + case 0x32: emc_num_burst_regs = 107; break; default: diff --git a/arch/arm/mach-tegra/tegra3_emc.h b/arch/arm/mach-tegra/tegra3_emc.h index 1b525c537c57..a27015639f44 100644 --- a/arch/arm/mach-tegra/tegra3_emc.h +++ b/arch/arm/mach-tegra/tegra3_emc.h @@ -41,6 +41,7 @@ struct tegra_emc_table { u32 emc_mode_reset; u32 emc_mode_1; u32 emc_mode_2; + u32 emc_dsr; }; struct clk; |