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| author | Scott Williams <scwilliams@nvidia.com> | 2011-05-26 13:20:13 -0700 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-05-31 18:19:17 -0700 |
| commit | c830be18de92cf690e66a5dea9a725a8467c62b6 (patch) | |
| tree | 940c11a0e8c9a24978a15501ed99a000301e5b4b | |
| parent | 109700c32b33c0738a00c0c14bfec144cfe0d827 (diff) | |
arm: tegra: Change Tegra3 L2 cache prefetch to next line
Change L2 cache prefetch offset from 8th line to next line.
Change-Id: Ie88008e2ab5a882235ae91d71d193e898ca67121
Reviewed-on: http://git-master/r/33195
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 5e4856b26e2b..2655d45efbb2 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -161,7 +161,7 @@ void __init tegra_init_cache(void) #endif /* Enable PL310 double line fill feature. */ - writel(((1<<30) | 7), p + L2X0_PREFETCH_OFFSET); + writel(((1<<30) | 0), p + L2X0_PREFETCH_OFFSET); #endif aux_ctrl = readl(p + L2X0_CACHE_TYPE); aux_ctrl = (aux_ctrl & 0x700) << (17-8); |