ARM: tegra: power: Update Tegra3 EMC DFS table

Change-Id: I29db9923c269c1c957342ca32ba0763daca05931
Reviewed-on: http://git-master/r/32685
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

1 files changed, 242 insertions, 2 deletions

diff --git a/arch/arm/mach-tegra/board-cardhu-memory.c b/arch/arm/mach-tegra/board-cardhu-memory.c
index d6548588ca09..52737aa80d48 100644
--- a/arch/arm/mach-tegra/board-cardhu-memory.c
+++ b/arch/arm/mach-tegra/board-cardhu-memory.c
@@ -22,6 +22,7 @@
 #include "board.h"
 #include "board-cardhu.h"
 #include "tegra3_emc.h"
+#include "fuse.h"
 
 
 static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
@@ -607,6 +608,241 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
 	},
 };
 
+static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
+	{
+		0x30,		/* Rev 3.0 */
+		400000,		/* SDRAM frequency */
+		{
+			0x00000012, /* EMC_RC */
+			0x0000003e, /* EMC_RFC */
+			0x0000000c, /* EMC_RAS */
+			0x00000004, /* EMC_RP */
+			0x00000002, /* EMC_R2W */
+			0x00000008, /* EMC_W2R */
+			0x00000002, /* EMC_R2P */
+			0x0000000a, /* EMC_W2P */
+			0x00000004, /* EMC_RD_RCD */
+			0x00000004, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000004, /* EMC_WDV */
+			0x00000006, /* EMC_QUSE */
+			0x00000004, /* EMC_QRST */
+			0x0000000b, /* EMC_QSAFE */
+			0x0000000c, /* EMC_RDV */
+			0x00000bf0, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000002fc, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000008, /* EMC_PDEX2WR */
+			0x00000008, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000008, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000044, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x0000000a, /* EMC_TCKE */
+			0x0000000c, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000c30, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00007088, /* EMC_FBIO_CFG5 */
+			0x001d0084, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00030000, /* EMC_DLL_XFORM_DQS0 */
+			0x00030000, /* EMC_DLL_XFORM_DQS1 */
+			0x00030000, /* EMC_DLL_XFORM_DQS2 */
+			0x00030000, /* EMC_DLL_XFORM_DQS3 */
+			0x00000010, /* EMC_DLL_XFORM_DQS4 */
+			0x00000010, /* EMC_DLL_XFORM_DQS5 */
+			0x00000010, /* EMC_DLL_XFORM_DQS6 */
+			0x00000010, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000018, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000018, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000018, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000018, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00048000, /* EMC_DLL_XFORM_DQ0 */
+			0x00048000, /* EMC_DLL_XFORM_DQ1 */
+			0x00048000, /* EMC_DLL_XFORM_DQ2 */
+			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0600013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc084, /* EMC_XM2CLKPADCTRL */
+			0x01f1f508, /* EMC_XM2COMPPADCTRL */
+			0x03037404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x07000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x01c0000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x800018c8, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000006, /* MC_EMEM_ARB_CFG */
+			0x80000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000009, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030202, /* MC_EMEM_ARB_DA_TURNS */
+			0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
+			0x7566120a, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		0x00000040,	/* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff,	/* EMC_AUTO_CAL_INTERVAL */
+		0x80000521,	/* Mode Register 0 */
+		0x80100002,	/* Mode Register 1 */
+		0x80200000,	/* Mode Register 2 */
+	},
+	{
+		0x30,		/* Rev 3.0 */
+		800000,		/* SDRAM frequency */
+		{
+			0x00000025, /* EMC_RC */
+			0x0000007e, /* EMC_RFC */
+			0x0000001a, /* EMC_RAS */
+			0x00000009, /* EMC_RP */
+			0x00000004, /* EMC_R2W */
+			0x0000000d, /* EMC_W2R */
+			0x00000004, /* EMC_R2P */
+			0x00000013, /* EMC_W2P */
+			0x00000009, /* EMC_RD_RCD */
+			0x00000009, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000007, /* EMC_WDV */
+			0x0000000b, /* EMC_QUSE */
+			0x00000009, /* EMC_QRST */
+			0x0000000b, /* EMC_QSAFE */
+			0x00000011, /* EMC_RDV */
+			0x00001820, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000012, /* EMC_PDEX2WR */
+			0x00000012, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x0000000f, /* EMC_AR2PDEN */
+			0x00000018, /* EMC_RW2PDEN */
+			0x00000088, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000014, /* EMC_TCKE */
+			0x00000018, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000007, /* EMC_TCLKSTABLE */
+			0x00000008, /* EMC_TCLKSTOP */
+			0x00001860, /* EMC_TREFBW */
+			0x0000000c, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00005088, /* EMC_FBIO_CFG5 */
+			0x00070084, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00010000, /* EMC_DLL_XFORM_DQS0 */
+			0x00010000, /* EMC_DLL_XFORM_DQS1 */
+			0x00010000, /* EMC_DLL_XFORM_DQS2 */
+			0x00010000, /* EMC_DLL_XFORM_DQS3 */
+			0x00010000, /* EMC_DLL_XFORM_DQS4 */
+			0x00010000, /* EMC_DLL_XFORM_DQS5 */
+			0x00010000, /* EMC_DLL_XFORM_DQS6 */
+			0x00010000, /* EMC_DLL_XFORM_DQS7 */
+			0x00010000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00010000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00010000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00010000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00010000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00010000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00010000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00010000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00018000, /* EMC_DLL_XFORM_DQ0 */
+			0x00018000, /* EMC_DLL_XFORM_DQ1 */
+			0x00018000, /* EMC_DLL_XFORM_DQ2 */
+			0x00018000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0600013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc084, /* EMC_XM2CLKPADCTRL */
+			0x01f1f508, /* EMC_XM2COMPPADCTRL */
+			0x07077404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x07000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x0180000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f11e1e, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000000c, /* MC_EMEM_ARB_CFG */
+			0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000013, /* MC_EMEM_ARB_TIMING_RC */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
+			0x08040202, /* MC_EMEM_ARB_DA_TURNS */
+			0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
+			0x72ac2414, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		0x00000040,	/* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff,	/* EMC_AUTO_CAL_INTERVAL */
+		0x80000d71,	/* Mode Register 0 */
+		0x80100002,	/* Mode Register 1 */
+		0x80200018,	/* Mode Register 2 */
+	},
+};
+
 int cardhu_emc_init(void)
 {
 	struct board_info board;
@@ -617,8 +853,12 @@ int cardhu_emc_init(void)
 	case BOARD_PM269:	/* LPDDR2 table is not ready, yet */
 		break;
 	default:
-		tegra_init_emc(cardhu_emc_tables_h5tc2g,
-			ARRAY_SIZE(cardhu_emc_tables_h5tc2g));
+		if (tegra_get_revision() == TEGRA_REVISION_A01)
+			tegra_init_emc(cardhu_emc_tables_h5tc2g,
+				ARRAY_SIZE(cardhu_emc_tables_h5tc2g));
+		else
+			tegra_init_emc(cardhu_emc_tables_h5tc2g_a2,
+				ARRAY_SIZE(cardhu_emc_tables_h5tc2g_a2));
 		break;
 	}