diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2011-05-12 09:44:45 +0530 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-05-18 10:34:49 -0700 |
| commit | 3655e9a4940bfa39ba103903f2e2f1d5f0cf7e2d (patch) | |
| tree | bee27e87932546bd8faf1307281922d5e1cac588 | |
| parent | 2c6fcec10ad5569670c97114dd880169efb8fed5 (diff) | |
ARM: tegra: clocks: sku limit for pclk
sclk max rate for AP25 is 300MHz and pclk is set as 1:2 to sclk.
pclk max rate changed to 150MHz for AP25.
Bug 821534
Change-Id: I6c6b30f0c9b2dd568e6171e9b6d88c8eef212ab7
Reviewed-on: http://git-master/r/31311
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 481acadff0cc..e1d85bb4f8be 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -2286,6 +2286,7 @@ static struct tegra_sku_rate_limit sku_limits[] = RATE_LIMIT("sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("virt_sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("hclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), + RATE_LIMIT("pclk", 150000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("avp.sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("bsea.sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("vde", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), |