diff options
| author | Wen Yi <wyi@nvidia.com> | 2011-05-10 12:00:42 -0700 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-07-21 18:01:54 -0700 |
| commit | bd8d778195bdcdf53fb1e6b9783ab08bf3b42e40 (patch) | |
| tree | cfe73ca56ff8b76d1baa72b0e872dc9afcdf1a55 | |
| parent | 1ebb8f9c02ae069cd2a6853b257cbc523a13ef5c (diff) | |
arm: tegra: manage graphics clock
Provides clock information for camera use cases to achieve
optimal power saving.
BUG 813159
Reviewed-on: http://git-master/r/31237
(cherry picked from commit 8180aabdb727b171ae9c49fbec991b3983ec87c8)
Change-Id: I19e99d39ff00bf0619d314854ce1b2fff670a8ff
Reviewed-on: http://git-master/r/37955
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/clock.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 13 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_dvfs.c | 3 |
3 files changed, 16 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index 6a1c5ba96a8a..21531895867d 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -44,6 +44,9 @@ #define MAX_SAME_LIMIT_SKU_IDS 16 +#define KHZ 1000 +#define MHZ 1000000 + struct clk; struct clk_mux_sel { diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index b4970e5251ea..cdba68976c03 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -373,12 +373,24 @@ static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate) return clk_set_rate(c->parent, rate); } +static long tegra2_super_clk_round_rate(struct clk *c, unsigned long rate) +{ + if (rate < c->min_rate) + return c->min_rate; + else if (rate > c->max_rate) + return c->max_rate; + else + return rate; +} + + static struct clk_ops tegra_super_ops = { .init = tegra2_super_clk_init, .enable = tegra2_super_clk_enable, .disable = tegra2_super_clk_disable, .set_parent = tegra2_super_clk_set_parent, .set_rate = tegra2_super_clk_set_rate, + .round_rate = tegra2_super_clk_round_rate, }; /* virtual cpu clock functions */ @@ -2296,6 +2308,7 @@ static struct tegra_sku_rate_limit sku_limits[] = RATE_LIMIT("bsea.sclk", 240000000, 0x04, 0x7, 0x08, 0x0F, 0x10), RATE_LIMIT("vde", 240000000, 0x04, 0x7, 0x08, 0x0F, 0x10), RATE_LIMIT("3d", 300000000, 0x04, 0x7, 0x08, 0x0F, 0x10), + RATE_LIMIT("mpe", 300000000, 0x04, 0x7, 0x08, 0x0F, 0x10), RATE_LIMIT("host1x", 108000000, 0x0F), diff --git a/arch/arm/mach-tegra/tegra2_dvfs.c b/arch/arm/mach-tegra/tegra2_dvfs.c index 3b65f13df211..4408a7044f4f 100644 --- a/arch/arm/mach-tegra/tegra2_dvfs.c +++ b/arch/arm/mach-tegra/tegra2_dvfs.c @@ -50,9 +50,6 @@ static const int core_speedo_nominal_millivolts[] = /* spedo_id 0, 1, 2 */ { 1225, 1225, 1300 }; -#define KHZ 1000 -#define MHZ 1000000 - static struct dvfs_rail tegra2_dvfs_rail_vdd_cpu = { .reg_id = "vdd_cpu", .max_millivolts = 1125, |