diff options
| author | Alex Frid <afrid@nvidia.com> | 2010-12-01 23:40:59 -0800 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2010-12-14 18:20:32 -0800 |
| commit | 2741470a650feb51647264ee6e1609471d28255e (patch) | |
| tree | 2a240365c463ff47e880b6ce3c3f240bbb351952 | |
| parent | a16216bd61a6200bef7f1bb3852c749eac6c4688 (diff) | |
[ARM/tegra] RM: Set minimum voltage limits
Set minimum CPU and core voltage limits required for
AP25/T25 reliability.
Bug 643434
Change-Id: I93735496d97cac742bdca3225b17f173f692821d
Reviewed-on: http://git-master/r/12603
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h | 15 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c | 7 |
2 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h index d211fdb61f41..ca0ed66caec7 100644 --- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h +++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h @@ -286,6 +286,21 @@ extern "C" /// Core voltage in suspend #define NVRM_AP20_SUSPEND_CORE_MV (1000) +/// Core and CPU voltage reliability requirements for some skus +#define NVRM_AP20_RELIABILITY_CORE_MV(sku) \ + ((((sku) == 23) || \ + ((sku) == 24) || \ + ((sku) == 20) || \ + ((sku) == 27) || \ + ((sku) == 28)) ? 1000 : 0) + +#define NVRM_AP20_RELIABILITY_CPU_MV(sku) \ + ((((sku) == 23) || \ + ((sku) == 24) || \ + ((sku) == 20) || \ + ((sku) == 27) || \ + ((sku) == 28)) ? 850 : 0) + /*****************************************************************************/ /** diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c index 4946a6442d93..4b6619ef93e5 100644 --- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c +++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c @@ -2360,10 +2360,16 @@ void NvRmPrivDvsInit(void) } else if (pDfs->hRm->ChipId.Id == 0x20) { + pDvs->MinCoreMv = NV_MAX(pDvs->MinCoreMv, + NVRM_AP20_RELIABILITY_CORE_MV(pDfs->hRm->ChipId.SKU)); + NV_ASSERT(pDvs->MinCoreMv <= pDvs->NominalCoreMv); pDvs->LowCornerCoreMv = NV_MAX(NVRM_AP20_LOW_CORE_MV, pDvs->MinCoreMv); pDvs->LowCornerCoreMv = NV_MIN(pDvs->LowCornerCoreMv, pDvs->NominalCoreMv); + pDvs->MinCpuMv = NV_MAX(pDvs->MinCpuMv, + NVRM_AP20_RELIABILITY_CPU_MV(pDfs->hRm->ChipId.SKU)); + NV_ASSERT(pDvs->MinCpuMv <= pDvs->NominalCpuMv); pDvs->LowCornerCpuMv = NV_MAX(NVRM_AP20_LOW_CPU_MV, pDvs->MinCpuMv); pDvs->LowCornerCpuMv = NV_MIN(pDvs->LowCornerCpuMv, pDvs->NominalCpuMv); @@ -2678,6 +2684,7 @@ void NvRmPrivDfsSuspend(NvOdmSocPowerState state) NvRmMilliVolts v = NV_MAX(pDvs->DvsCorner.SystemMv, NV_MAX(pDvs->DvsCorner.EmcMv, pDvs->DvsCorner.ModulesMv)); + v = NV_MAX(v, pDvs->MinCoreMv); // If CPU rail returns to default level by PMU underneath DVFS // need to synchronize voltage after LP1 same way as after LP2 |