diff options
| author | Hoang Pham <hopham@nvidia.com> | 2010-10-11 08:58:35 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2010-10-12 15:23:25 -0700 |
| commit | d15bba7c21d6cbe34ec44394d3b87e7a34d6469a (patch) | |
| tree | 907e5126c7a4a517ef8456cb7fca5aaba9461696 | |
| parent | 9b86e864f42d2f87f2681fc3a6b89b42feca3aae (diff) | |
[arm/tegra] Tristate pta pingroup
The pta pingroup is in NORMAL at POR. Tristating this pingroup at init
by default to reduce the power when enter LP0 mode
Bug 740749
Change-Id: I5ff86c3ddbeb5c608eaee9e11db462acff8ea222
Reviewed-on: http://git-master/r/8109
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c index 145a36e50fac..d58d892636b6 100644 --- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c +++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c @@ -324,5 +324,7 @@ NvRmAp20GetStraps( void NvRmAp20SetDefaultTristate(NvRmDeviceHandle hDevice) { tegra_pinmux_set_vddio_tristate(TEGRA_VDDIO_NAND, TEGRA_TRI_TRISTATE); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_PTA, TEGRA_TRI_NORMAL); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_PTA, TEGRA_TRI_TRISTATE); } |