diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2010-09-23 12:30:09 +0530 |
|---|---|---|
| committer | Bharat Nihalani <bnihalani@nvidia.com> | 2010-09-23 20:46:18 -0700 |
| commit | f1dc67120328e345dd5dfd5c96fba85fd9915690 (patch) | |
| tree | 7d7b218b1444ff39418ed6665376fee9eeda7778 | |
| parent | f62d5b35d65e87432575a4e637400899cbfbb940 (diff) | |
[odm] whistler pinmux: Fixing UartA pinmux option for RIL
RIL interacing with UARTA is using the 4 line.
The correct configuration for this interface is Config6.
Currently it is config1 which is causing the issue on other
pin operation.
Fixing this issue.
bug 710711
Change-Id: I68e426de4597f87d832fb934e2cf6120e898b3de
Reviewed-on: http://git-master/r/7100
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_pinmux.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_pinmux.c b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_pinmux.c index 1e9aeef4e584..a9bc444f6a9c 100644 --- a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_pinmux.c +++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_pinmux.c @@ -55,6 +55,14 @@ static const NvU32 s_NvOdmPinMuxConfig_Uart_Hsi_Ulpi[] = { 0, // UART-E function disabled: pins used by WiFi (SDIO1) }; +static const NvU32 s_NvOdmPinMuxConfig_Uart_Ril_Emp[] = { + NvOdmUartPinMap_Config6, // Instance 0: UART-A is mapped to UAA pin group. + NvOdmUartPinMap_Config1, // Instance 1: UART-B + NvOdmUartPinMap_Config1, // Instance 2: UART-C + 0, // UART-D function disabled: pins used by BB (SPI1) + 0, // UART-E function disabled: pins used by WiFi (SDIO1) +}; + static const NvU32 s_NvOdmPinMuxConfig_Uart[] = { NvOdmUartPinMap_Config1, @@ -336,6 +344,11 @@ NvOdmQueryPinMux( *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Uart_Hsi_Ulpi; *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Uart_Hsi_Ulpi); } + else if (Ril == TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW) + { + *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Uart_Ril_Emp; + *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Uart_Ril_Emp); + } else { *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Uart; |