Merge remote branch 'origin/tegra-2010-09' into HEAD

8 files changed, 385 insertions, 21 deletions

diff --git a/arch/arm/mach-tegra/board-nvodm.c b/arch/arm/mach-tegra/board-nvodm.c
index ae04dcdfcdeb..bb3efa86bf20 100755
--- a/arch/arm/mach-tegra/board-nvodm.c
+++ b/arch/arm/mach-tegra/board-nvodm.c
@@ -501,6 +501,9 @@ static void __init tegra_setup_hsuart(void)
 		if (i==dbg_id)
 			continue;
 
+		if (odm_table[i] == 0)
+			continue;
+
 		plat = &tegra_uart_platform[i];
 
 		snprintf(name, sizeof(name), "%s.%d",
diff --git a/arch/arm/mach-tegra/clock_nvrm.c b/arch/arm/mach-tegra/clock_nvrm.c
index 598c001179a2..925c8fb6ad18 100644
--- a/arch/arm/mach-tegra/clock_nvrm.c
+++ b/arch/arm/mach-tegra/clock_nvrm.c
@@ -102,8 +102,10 @@ static int tegra_periph_clk_enable(struct clk *c)
 
 	/* max out emc when 3d is on */
 	if (NVRM_MODULE_ID_MODULE(c->module) == NvRmModuleID_3D) {
-		NvRmPowerBusyHint(s_hRmGlobal, NvRmDfsClockId_Emc, clk_pwr_client,
-				0xffffffff, NvRmFreqMaximum);
+		NvRmDfsBusyHint hint =
+			{NvRmDfsClockId_Emc, 0xffffffff, NvRmFreqMaximum, true};
+		NvRmPowerBusyHintMulti(s_hRmGlobal, clk_pwr_client, &hint, 1,
+			NvRmDfsBusyHintSyncMode_Async);
 	}
 
 	return 0;
@@ -114,7 +116,9 @@ static void tegra_periph_clk_disable(struct clk *c)
 	NvError e;
 
 	if (NVRM_MODULE_ID_MODULE(c->module) == NvRmModuleID_3D) {
-		NvRmPowerBusyHint(s_hRmGlobal, NvRmDfsClockId_Emc, clk_pwr_client, 0, 0);
+		NvRmDfsBusyHint hint = {NvRmDfsClockId_Emc, 0, 0, true};
+		NvRmPowerBusyHintMulti(s_hRmGlobal, clk_pwr_client, &hint, 1,
+			NvRmDfsBusyHintSyncMode_Async);
 	}
 
 	e = NvRmPowerModuleClockControl(s_hRmGlobal, c->module,
diff --git a/arch/arm/mach-tegra/nvddk/nvddk_usbphy_priv.h b/arch/arm/mach-tegra/nvddk/nvddk_usbphy_priv.h
index 3b4c0e074552..3ed53a20dfb4 100644
--- a/arch/arm/mach-tegra/nvddk/nvddk_usbphy_priv.h
+++ b/arch/arm/mach-tegra/nvddk/nvddk_usbphy_priv.h
@@ -63,7 +63,7 @@ enum {USB_HW_MIN_SYSTEM_FREQ_KH = 100000};
 /**
  * Minimum cpu frequency required for USB for optimal performance
  */
-enum {USB_HW_MIN_CPU_FREQ_KH = 200000};
+enum {USB_HW_MIN_CPU_FREQ_KH = 300000};
 
 /**
  * Wait time(1 second) for controller H/W status to change before giving up.
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c
index 93fbdc2fc9a5..810453f8e00e 100644
--- a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c
@@ -51,6 +51,7 @@
 
 #define BOARD_ID_WHISTLER_E1108 0x0B08
 #define BOARD_ID_WHISTLER_E1109 0x0B09
+#define BOARD_ID_WHISTLER_E1112 0x0B0C
 #define BOARD_ID_WHISTLER_PMU_E1116 0x0B10
 #define BOARD_ID_WHISTLER_MOTHERBOARD_E1120 0xB14
 #define BOARD_ID_VOYAGER_MAINBOARD_E1215    0xC0F
@@ -889,6 +890,334 @@ static const NvOdmSdramControllerConfigAdv s_NvOdmE1108ElpidaEmcConfigTable[] =
     }
 };
 
+static const NvOdmSdramControllerConfigAdv s_NvOdmE1112SamsungEmcConfigTable[] =
+{
+    {
+                  0x20,   /* Rev 2.0 */
+                 18000,   /* SDRAM frquency */
+                   900,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000002,   /* RC */
+            0x00000006,   /* RFC */
+            0x00000003,   /* RAS */
+            0x00000003,   /* RP */
+            0x00000006,   /* R2W */
+            0x00000004,   /* W2R */
+            0x00000002,   /* R2P */
+            0x0000000b,   /* W2P */
+            0x00000003,   /* RD_RCD */
+            0x00000003,   /* WR_RCD */
+            0x00000002,   /* RRD */
+            0x00000002,   /* REXT */
+            0x00000003,   /* WDV */
+            0x00000005,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000008,   /* QSAFE */
+            0x0000000c,   /* RDV */
+            0x00000038,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000003,   /* PCHG2PDEN */
+            0x00000008,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000b,   /* RW2PDEN */
+            0x00000003,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x00000008,   /* TFAW */
+            0x00000004,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x0000004b,   /* TREFBW */
+            0x00000004,   /* QUSE_EXTRA */
+            0x00000003,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000082,   /* FBIO_CFG5 */
+            0xa06804ae,   /* CFG_DIG_DLL */
+            0x00004810,   /* DLL_XFORM_DQS */
+            0x00000000,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x00000002,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    },
+    {
+                  0x20,   /* Rev 2.0 */
+                 27000,   /* SDRAM frquency */
+                   950,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000002,   /* RC */
+            0x00000006,   /* RFC */
+            0x00000003,   /* RAS */
+            0x00000003,   /* RP */
+            0x00000006,   /* R2W */
+            0x00000004,   /* W2R */
+            0x00000002,   /* R2P */
+            0x0000000b,   /* W2P */
+            0x00000003,   /* RD_RCD */
+            0x00000003,   /* WR_RCD */
+            0x00000002,   /* RRD */
+            0x00000002,   /* REXT */
+            0x00000003,   /* WDV */
+            0x00000005,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000008,   /* QSAFE */
+            0x0000000c,   /* RDV */
+            0x00000054,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000003,   /* PCHG2PDEN */
+            0x00000008,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000b,   /* RW2PDEN */
+            0x00000004,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x00000008,   /* TFAW */
+            0x00000004,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x00000071,   /* TREFBW */
+            0x00000004,   /* QUSE_EXTRA */
+            0x00000003,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000082,   /* FBIO_CFG5 */
+            0xa06804ae,   /* CFG_DIG_DLL */
+            0x00004810,   /* DLL_XFORM_DQS */
+            0x00000000,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x00000003,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    },
+    {
+                  0x20,   /* Rev 2.0 */
+                 54000,   /* SDRAM frquency */
+                  1000,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000004,   /* RC */
+            0x00000008,   /* RFC */
+            0x00000003,   /* RAS */
+            0x00000003,   /* RP */
+            0x00000006,   /* R2W */
+            0x00000004,   /* W2R */
+            0x00000002,   /* R2P */
+            0x0000000b,   /* W2P */
+            0x00000003,   /* RD_RCD */
+            0x00000003,   /* WR_RCD */
+            0x00000002,   /* RRD */
+            0x00000002,   /* REXT */
+            0x00000003,   /* WDV */
+            0x00000006,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000008,   /* QSAFE */
+            0x0000000c,   /* RDV */
+            0x000000a8,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000003,   /* PCHG2PDEN */
+            0x00000008,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000b,   /* RW2PDEN */
+            0x00000008,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x00000008,   /* TFAW */
+            0x00000004,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x000000e1,   /* TREFBW */
+            0x00000005,   /* QUSE_EXTRA */
+            0x00000000,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000082,   /* FBIO_CFG5 */
+            0xa06804ae,   /* CFG_DIG_DLL */
+            0x00004810,   /* DLL_XFORM_DQS */
+            0x00000000,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x00000005,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    },
+    {
+                  0x20,   /* Rev 2.0 */
+                108000,   /* SDRAM frquency */
+                  1000,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000007,   /* RC */
+            0x0000000f,   /* RFC */
+            0x00000005,   /* RAS */
+            0x00000003,   /* RP */
+            0x00000006,   /* R2W */
+            0x00000004,   /* W2R */
+            0x00000002,   /* R2P */
+            0x0000000b,   /* W2P */
+            0x00000003,   /* RD_RCD */
+            0x00000003,   /* WR_RCD */
+            0x00000002,   /* RRD */
+            0x00000002,   /* REXT */
+            0x00000003,   /* WDV */
+            0x00000006,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000008,   /* QSAFE */
+            0x0000000c,   /* RDV */
+            0x0000017f,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000003,   /* PCHG2PDEN */
+            0x00000008,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000b,   /* RW2PDEN */
+            0x00000010,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x00000008,   /* TFAW */
+            0x00000004,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x000001c2,   /* TREFBW */
+            0x00000005,   /* QUSE_EXTRA */
+            0x00000001,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000082,   /* FBIO_CFG5 */
+            0xa06804ae,   /* CFG_DIG_DLL */
+            0x007f9010,   /* DLL_XFORM_DQS */
+            0x00000000,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x0000000a,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    },
+    {
+                  0x20,   /* Rev 2.0 */
+                150000,   /* SDRAM frquency */
+                  1000,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000009,   /* RC */
+            0x00000014,   /* RFC */
+            0x00000007,   /* RAS */
+            0x00000003,   /* RP */
+            0x00000006,   /* R2W */
+            0x00000004,   /* W2R */
+            0x00000002,   /* R2P */
+            0x0000000b,   /* W2P */
+            0x00000003,   /* RD_RCD */
+            0x00000003,   /* WR_RCD */
+            0x00000002,   /* RRD */
+            0x00000002,   /* REXT */
+            0x00000003,   /* WDV */
+            0x00000006,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000008,   /* QSAFE */
+            0x0000000c,   /* RDV */
+            0x0000021f,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000003,   /* PCHG2PDEN */
+            0x00000008,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000b,   /* RW2PDEN */
+            0x00000015,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x00000008,   /* TFAW */
+            0x00000004,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x00000270,   /* TREFBW */
+            0x00000005,   /* QUSE_EXTRA */
+            0x00000001,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000082,   /* FBIO_CFG5 */
+            0xa04c04ae,   /* CFG_DIG_DLL */
+            0x007fe010,   /* DLL_XFORM_DQS */
+            0x00000000,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x0000000e,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    },
+    {
+                  0x20,   /* Rev 2.0 */
+                300000,   /* SDRAM frquency */
+                  1200,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000012,   /* RC */
+            0x00000027,   /* RFC */
+            0x0000000d,   /* RAS */
+            0x00000006,   /* RP */
+            0x00000007,   /* R2W */
+            0x00000005,   /* W2R */
+            0x00000003,   /* R2P */
+            0x0000000b,   /* W2P */
+            0x00000006,   /* RD_RCD */
+            0x00000006,   /* WR_RCD */
+            0x00000003,   /* RRD */
+            0x00000003,   /* REXT */
+            0x00000003,   /* WDV */
+            0x00000007,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000009,   /* QSAFE */
+            0x0000000d,   /* RDV */
+            0x0000045f,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000004,   /* PDEX2WR */
+            0x00000004,   /* PDEX2RD */
+            0x00000006,   /* PCHG2PDEN */
+            0x00000008,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000f,   /* RW2PDEN */
+            0x0000002a,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x0000000f,   /* TFAW */
+            0x00000007,   /* TRPAB */
+            0x00000007,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x000004e0,   /* TREFBW */
+            0x00000006,   /* QUSE_EXTRA */
+            0x00000002,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000282,   /* FBIO_CFG5 */
+            0xe03c048b,   /* CFG_DIG_DLL */
+            0x00000010,   /* DLL_XFORM_DQS */
+            0x00000000,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x0000001b,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    }
+};
+
 
 // Wake Events
 static NvOdmWakeupPadInfo s_NvOdmWakeupPadInfo[] =
@@ -991,6 +1320,20 @@ static NvBool NvOdmIsE1108Elpida(void)
     return NvOdmIsBoardPresent(s_WhistlerE1108Elpida,
                                NV_ARRAY_SIZE(s_WhistlerE1108Elpida));
 }
+
+static NvBool NvOdmIsE1112Samsung(void)
+{
+    // A list of Whistler E1112 processor boards with Samsung LPDDR2
+    // charcterized by s_NvOdmE1112SamsungEmcConfigTable (fill in
+    // ID/SKU/FAB fields, revision fields are ignored)
+    static const NvOdmBoardInfo s_WhistlerE1112Samsung[] =
+    {
+        // ID                      SKU     FAB   Rev            Minor Rev
+        { BOARD_ID_WHISTLER_E1112, 0x0B00, 0x00, BOARD_REV_ALL, BOARD_REV_ALL}
+    };
+    return NvOdmIsBoardPresent(s_WhistlerE1112Samsung,
+                               NV_ARRAY_SIZE(s_WhistlerE1112Samsung));
+}
 #endif
 
 static NvBool NvOdmIsCpuRailPreserved(void)
@@ -1364,6 +1707,14 @@ NvOdmQuerySdramControllerConfigGet(NvU32 *pEntries, NvU32 *pRevision)
             *pEntries = NV_ARRAY_SIZE(s_NvOdmE1108ElpidaEmcConfigTable);
         return (const void*)s_NvOdmE1108ElpidaEmcConfigTable;
     }
+    else if (NvOdmIsE1112Samsung())
+    {
+        if (pRevision)
+            *pRevision = s_NvOdmE1112SamsungEmcConfigTable[0].Revision;
+        if (pEntries)
+            *pEntries = NV_ARRAY_SIZE(s_NvOdmE1112SamsungEmcConfigTable);
+        return (const void*)s_NvOdmE1112SamsungEmcConfigTable;
+    }
 #endif
     if (pEntries)
         *pEntries = 0;
diff --git a/drivers/serial/tegra_hsuart.c b/drivers/serial/tegra_hsuart.c
index f179d098cdc4..353a43bc3906 100755
--- a/drivers/serial/tegra_hsuart.c
+++ b/drivers/serial/tegra_hsuart.c
@@ -668,8 +668,8 @@ static void tegra_uart_hw_deinit(struct tegra_uart_port *t)
 	/* Disable interrupts */
 	uart_writeb(t, 0, UART_IER);
 
-	while ((uart_readb(t, UART_LSR) & UART_LSR_TEMT) != UART_LSR_TEMT);
-		udelay(2000);
+	/* TBD: why this delay is needed */
+	udelay(200);
 
 	/* Reset the Rx and Tx FIFOs */
 	fcr = t->fcr_shadow;
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index 845d98c0b5c6..209dae73408d 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -79,8 +79,6 @@
 
 #define BULK_BUFFER_SIZE           4096
 
-/* flush after every 4 meg of writes to avoid excessive block level caching */
-#define MAX_UNFLUSHED_BYTES (4 * 1024 * 1024)
 
 /*-------------------------------------------------------------------------*/
 
@@ -229,7 +227,6 @@ struct lun {
 	struct file	*filp;
 	loff_t		file_length;
 	loff_t		num_sectors;
-	unsigned int unflushed_bytes;
 
 	unsigned int	ro : 1;
 	unsigned int	prevent_medium_removal : 1;
@@ -396,7 +393,7 @@ static struct fsg_dev			*the_fsg;
 
 static void	close_backing_file(struct fsg_dev *fsg, struct lun *curlun);
 static void	close_all_backing_files(struct fsg_dev *fsg);
-static int fsync_sub(struct lun *curlun);
+
 
 /*-------------------------------------------------------------------------*/
 
@@ -1046,13 +1043,6 @@ static int do_write(struct fsg_dev *fsg)
 			amount_left_to_write -= nwritten;
 			fsg->residue -= nwritten;
 
-#ifdef MAX_UNFLUSHED_BYTES
-			curlun->unflushed_bytes += nwritten;
-			if (curlun->unflushed_bytes >= MAX_UNFLUSHED_BYTES) {
-				fsync_sub(curlun);
-				curlun->unflushed_bytes = 0;
-			}
-#endif
 			/* If an error occurred, report it and its position */
 			if (nwritten < amount) {
 				curlun->sense_data = SS_WRITE_ERROR;
@@ -2557,7 +2547,6 @@ static int open_backing_file(struct fsg_dev *fsg, struct lun *curlun,
 	curlun->ro = ro;
 	curlun->filp = filp;
 	curlun->file_length = size;
-	curlun->unflushed_bytes = 0;
 	curlun->num_sectors = num_sectors;
 	LDBG(curlun, "open backing file: %s size: %lld num_sectors: %lld\n",
 			filename, size, num_sectors);
diff --git a/drivers/video/tegra/host/nvhost_acm.c b/drivers/video/tegra/host/nvhost_acm.c
index 360774b72bb6..4628306c02a8 100644
--- a/drivers/video/tegra/host/nvhost_acm.c
+++ b/drivers/video/tegra/host/nvhost_acm.c
@@ -50,8 +50,7 @@ static void powerdown_handler(struct work_struct *work)
 	struct nvhost_module *mod;
 	mod = container_of(to_delayed_work(work), struct nvhost_module, powerdown);
 	mutex_lock(&mod->lock);
-	BUG_ON(!mod->powered);
-	if (atomic_read(&mod->refcount) == 0) {
+	if ((atomic_read(&mod->refcount) == 0) && mod->powered){
 		int i;
 		if (mod->func)
 			mod->func(mod, NVHOST_POWER_ACTION_OFF);
diff --git a/drivers/video/tegra/host/nvhost_dev.c b/drivers/video/tegra/host/nvhost_dev.c
index bc63d24c73b7..334e9b6acdb9 100644
--- a/drivers/video/tegra/host/nvhost_dev.c
+++ b/drivers/video/tegra/host/nvhost_dev.c
@@ -567,7 +567,10 @@ static void power_host(struct nvhost_module *mod, enum nvhost_power_action actio
 
 	if (action == NVHOST_POWER_ACTION_ON) {
 		nvhost_intr_start(&dev->intr, clk_get_rate(mod->clk[0]));
-		nvhost_syncpt_reset(&dev->syncpt);
+		/* don't do it, as display may have changed syncpt
+		 * after the last save
+		 * nvhost_syncpt_reset(&dev->syncpt);
+		 */
 	} else if (action == NVHOST_POWER_ACTION_OFF) {
 		int i;
 		for (i = 0; i < NVHOST_NUMCHANNELS; i++)
@@ -723,13 +726,28 @@ static int nvhost_suspend(struct platform_device *pdev, pm_message_t state)
 	struct nvhost_dev *host = platform_get_drvdata(pdev);
 	dev_info(&pdev->dev, "suspending\n");
 	nvhost_module_suspend(&host->mod);
+	clk_enable(host->mod.clk[0]);
+	nvhost_syncpt_save(&host->syncpt);
+	clk_disable(host->mod.clk[0]);
 	dev_info(&pdev->dev, "suspended\n");
 	return 0;
 }
 
+static int nvhost_resume(struct platform_device *pdev)
+{
+	struct nvhost_dev *host = platform_get_drvdata(pdev);
+	dev_info(&pdev->dev, "resuming\n");
+	clk_enable(host->mod.clk[0]);
+	nvhost_syncpt_reset(&host->syncpt);
+	clk_disable(host->mod.clk[0]);
+	dev_info(&pdev->dev, "resumed\n");
+	return 0;
+}
+
 static struct platform_driver nvhost_driver = {
 	.remove = __exit_p(nvhost_remove),
 	.suspend = nvhost_suspend,
+	.resume = nvhost_resume,
 	.driver = {
 		.owner = THIS_MODULE,
 		.name = DRIVER_NAME