[ARM/tegra] RM: Updated HDMI PLLD settings.

Separated PLLD and PLLC HDMI settings. Changed PLLD settings to
increase comparison frequency for 12MHz and 26MHz reference clocks.
Kept PLLD settings for other reference clocks and all PLLC settings
unchanged. Idempotent PLL configuration clean up.

Bug 719667

Change-Id: I882ca2d8a98618518099a5b9482526d5556ba8ea
Reviewed-on: http://git-master/r/6340
Tested-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

2 files changed, 52 insertions, 25 deletions

diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
index e6723ea7c321..27ce11605808 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
@@ -431,7 +431,7 @@ NvRmPrivAp15PllSet(
     {   // Compiler failed to generate correct code for the base fields
         // concatenation without the split below
         volatile NvU32 prebase =
-            NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, ENABLE) |
+            NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, DISABLE) |
             NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_ENABLE, ENABLE) |
             NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_REF_DIS, REF_ENABLE);
         base = prebase |
@@ -444,23 +444,29 @@ NvRmPrivAp15PllSet(
     // If PLL is not bypassed, and new configurations is the same as the old
     // one - exit without overwriting h/w. Otherwise, bypass PLL before
     // changing configuration.
-    if (NV_DRF_VAL(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, old_base) ==
-        CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DISABLE)
+    if ((base == old_base) && (misc == old_misc))
     {
-        old_base = NV_FLD_SET_DRF_DEF(
-            CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, ENABLE, old_base);
-        if ((base == old_base) && (misc == old_misc))
-        {
-            NvRmPrivPllFreqUpdate(hRmDevice, pCinfo);
-            return;
-        }
-        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
-                pCinfo->PllBaseOffset, old_base);
+        NvRmPrivPllFreqUpdate(hRmDevice, pCinfo);
+        return;
     }
+    old_base = NV_FLD_SET_DRF_DEF(
+        CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, ENABLE, old_base);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            pCinfo->PllBaseOffset, old_base);
 
     // Configure and enable PLL, keep it bypassed
-    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllMiscOffset, misc);
-    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllBaseOffset, base);
+    base = NV_FLD_SET_DRF_DEF(
+        CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, ENABLE, base);
+    base = NV_FLD_SET_DRF_DEF(
+        CLK_RST_CONTROLLER, PLLP_BASE, PLLP_ENABLE, DISABLE, base);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            pCinfo->PllBaseOffset, base);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            pCinfo->PllMiscOffset, misc);
+    base = NV_FLD_SET_DRF_DEF(
+        CLK_RST_CONTROLLER, PLLP_BASE, PLLP_ENABLE, ENABLE, base);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            pCinfo->PllBaseOffset, base);
 
     // Wait for PLL to stabilize and switch to PLL output
     NV_ASSERT(StableDelayUs);
@@ -468,8 +474,10 @@ NvRmPrivAp15PllSet(
         StableDelayUs = delay;
     NvOsWaitUS(StableDelayUs);
 
-    base = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, DISABLE, base);
-    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllBaseOffset, base);
+    base = NV_FLD_SET_DRF_DEF(
+        CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, DISABLE, base);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            pCinfo->PllBaseOffset, base);
     NvRmPrivPllFreqUpdate(hRmDevice, pCinfo);
 }
 
@@ -683,7 +691,7 @@ NvRmPrivAp15PllConfigureSimple(
 
 // Fixed list of PLL HDMI configurations for different reference frequencies
 // arranged according to CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_FIELD enum
-static const NvRmPllFixedConfig s_Ap15HdmiPllConfigurations[] =
+static const NvRmPllFixedConfig s_Ap15HdmiPllD_Configurations[] =
 {
     NVRM_PLLHD_AT_13MHZ,
     NVRM_PLLHD_AT_19MHZ,
@@ -691,6 +699,15 @@ static const NvRmPllFixedConfig s_Ap15HdmiPllConfigurations[] =
     NVRM_PLLHD_AT_26MHZ
 };
 
+static const NvRmPllFixedConfig s_Ap15HdmiPllC_Configurations[] =
+{
+    NVRM_PLLHC_AT_13MHZ,
+    NVRM_PLLHC_AT_19MHZ,
+    NVRM_PLLHC_AT_12MHZ,
+    NVRM_PLLHC_AT_26MHZ
+};
+
+
 void
 NvRmPrivAp15PllConfigureHdmi(
     NvRmDeviceHandle hRmDevice,
@@ -702,15 +719,20 @@ NvRmPrivAp15PllConfigureHdmi(
     const NvRmPllClockInfo* pCinfo =
         NvRmPrivGetClockSourceHandle(PllId)->pInfo.pPll;
 
-    // Only PLLD or PLLC should be configured here
-    NV_ASSERT((PllId == NvRmClockSource_PllD0) ||
-              (PllId == NvRmClockSource_PllC0));
-
     reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
                   CLK_RST_CONTROLLER_OSC_CTRL_0);
-    HdmiConfig = s_Ap15HdmiPllConfigurations[NV_DRF_VAL(
-        CLK_RST_CONTROLLER, OSC_CTRL, OSC_FREQ, reg)];
 
+    if (PllId == NvRmClockSource_PllD0)
+        HdmiConfig = s_Ap15HdmiPllD_Configurations[NV_DRF_VAL(
+            CLK_RST_CONTROLLER, OSC_CTRL, OSC_FREQ, reg)];
+    else if (PllId == NvRmClockSource_PllC0)
+        HdmiConfig = s_Ap15HdmiPllC_Configurations[NV_DRF_VAL(
+            CLK_RST_CONTROLLER, OSC_CTRL, OSC_FREQ, reg)];
+    else
+    {
+        NV_ASSERT(!"Only PLLD or PLLC should be configured here");
+        return;
+    }
     NvRmPrivAp15PllSet(hRmDevice, pCinfo, HdmiConfig.M, HdmiConfig.N,
                        HdmiConfig.P, (NvU32)-1, 0, 0, NV_TRUE, 0);
     *pPllOutKHz = NvRmPrivGetClockSourceFreq(pCinfo->SourceId);
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h
index 21e61b4ec459..2658b15b12cf 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h
@@ -198,10 +198,15 @@ typedef struct NvRmPllFixedConfigRec
  * This difference in source frequency is will be taken care by Display and
  * HDMI clock dividers.
  */
-#define NVRM_PLLHD_AT_12MHZ { 594000, 12, 594, 0, 0}
+#define NVRM_PLLHD_AT_12MHZ { 594000,  4, 198, 0, 0}
 #define NVRM_PLLHD_AT_13MHZ { 594000, 13, 594, 0, 0}
 #define NVRM_PLLHD_AT_19MHZ { 594000, 16, 495, 0, 0}
-#define NVRM_PLLHD_AT_26MHZ { 594000, 26, 594, 0, 0}
+#define NVRM_PLLHD_AT_26MHZ { 594000, 13, 297, 0, 0}
+
+#define NVRM_PLLHC_AT_12MHZ { 594000, 12, 594, 0, 0}
+#define NVRM_PLLHC_AT_13MHZ { 594000, 13, 594, 0, 0}
+#define NVRM_PLLHC_AT_19MHZ { 594000, 16, 495, 0, 0}
+#define NVRM_PLLHC_AT_26MHZ { 594000, 26, 594, 0, 0}
 
 // Display divider is part of the display module and it is not described
 // in central module clock information table. Hence, need this define.