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authorRakesh Kumar <krakesh@nvidia.com>2010-08-17 00:26:28 +0530
committerBharat Nihalani <bnihalani@nvidia.com>2010-08-27 03:28:51 -0700
commit4d8632b1f370c9d7862653d0190cc2da1c2debe0 (patch)
treedb8b305d8409371522acee25c68c90f0443be126
parent8e5d7631489757b0b5bea1b129aed8c1b5712130 (diff)
[arm/tegra] comms: move 32KHz clock initialization
32KHz clock is required for bcm4329 wifi, bluetooth and gps. wifi odm is not correct place for it. Change-Id: I2613236c5cff918b51921609d942568865324a00 Reviewed-on: http://git-master/r/5199 Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> Tested-by: Rakesh Kumar <krakesh@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/board-generic.c18
-rw-r--r--arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_sdio.c15
2 files changed, 18 insertions, 15 deletions
diff --git a/arch/arm/mach-tegra/board-generic.c b/arch/arm/mach-tegra/board-generic.c
index 7ad72114c86a..1a291690d1db 100644
--- a/arch/arm/mach-tegra/board-generic.c
+++ b/arch/arm/mach-tegra/board-generic.c
@@ -210,6 +210,23 @@ void __init i2c_device_setup(void)
ARRAY_SIZE(bus3_i2c_devices));
}
+// enable 32Khz clock used by bcm4329 wifi, bluetooth and gps
+static void __init tegra_setup_32khz_clock(void)
+{
+ int RequestedPeriod, ReturnedPeriod;
+ NvOdmServicesPwmHandle hOdmPwm = NULL;
+
+ hOdmPwm = NvOdmPwmOpen();
+ if (!hOdmPwm) {
+ pr_err("%s: failed to open NvOdmPwmOpen\n", __func__);
+ return;
+ }
+ RequestedPeriod = 0;
+ NvOdmPwmConfig(hOdmPwm, NvOdmPwmOutputId_Blink,
+ NvOdmPwmMode_Blink_32KHzClockOutput, 0, &RequestedPeriod, &ReturnedPeriod);
+ NvOdmPwmClose(hOdmPwm);
+}
+
extern void __init tegra_setup_nvodm(bool standard_i2c, bool standard_spi);
extern void __init tegra_register_socdev(void);
@@ -293,6 +310,7 @@ static void __init tegra_ventana_init(void)
#endif
do_system_init(false, true);
i2c_device_setup();
+ tegra_setup_32khz_clock();
}
static void __init tegra_generic_init(void)
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_sdio.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_sdio.c
index 2a67cbaf91e0..a837a3d3524b 100644
--- a/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_sdio.c
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_sdio.c
@@ -71,8 +71,6 @@ static void NvOdmSetPowerOnSdio(NvOdmSdioHandle pDevice, NvBool enable)
static NvBool SdioOdmWlanPower(NvOdmSdioHandle hOdmSdio, NvBool IsEnable)
{
- NvU32 RequestedPeriod, ReturnedPeriod;
- NvOdmServicesPwmHandle hOdmPwm = NULL;
if (IsEnable)
{
// Wlan Power On Reset Sequence
@@ -82,19 +80,6 @@ static NvBool SdioOdmWlanPower(NvOdmSdioHandle hOdmSdio, NvBool IsEnable)
NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hPwrPin, 0x1);
NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hResetPin, 0x1);
NvOdmOsSleepMS(200);
-
- // Enable 32KHz clock out
- hOdmPwm = NvOdmPwmOpen();
- if (!hOdmPwm)
- {
- NvOsDebugPrintf("sdio_odm: NvOdmPwmOpen failed\n");
- return NV_FALSE;
- }
- RequestedPeriod = 0;
- NvOdmPwmConfig(hOdmPwm, NvOdmPwmOutputId_Blink,
- NvOdmPwmMode_Blink_32KHzClockOutput,
- 0, &RequestedPeriod, &ReturnedPeriod);
- NvOdmPwmClose(hOdmPwm);
}
else
{