diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2010-08-02 12:52:22 -0700 |
|---|---|---|
| committer | Scott Williams <scwilliams@nvidia.com> | 2010-08-02 17:48:35 -0700 |
| commit | f8118de93735b6b957437c548e2f025b25237ffc (patch) | |
| tree | 598f6c12f053c9eeefbdb5ebade8364465e35911 | |
| parent | 3a9a23977f0bda9e63c7e13e9cdea23e262db875 (diff) | |
[arm/tegra] Don't try to enable CoreSight on non-running CPUs
On exit from LP2, __enable_coresite_access was called to reset the
CoreSight interface and re-enable access on all CPUs. However, only
CPU0 would actually be running at the time (the other CPU would still
be held in reset). The attempt to unlock CoreSight on the non-running
CPU would cause a stall on the APB bus while the CoreSight access
timed out. The APB stall would cause SLINK DMA receiver overruns.
Rather than attempting to unlock CoreSight access up front for every
CPU, each CPU is now responsible for unlocking it's own access when
it starts up.
Bug 703311
Change-Id: Ie4611423ed72eb1cd0dbc8b7851f7a047bcffa14
Reviewed-on: http://git-master/r/4683
Reviewed-by: Gary King <gking@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Tested-by: Michael Hsu <mhsu@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/headsmp-t2.S | 1 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/headsmp.S | 14 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/power-macros.S | 6 |
3 files changed, 12 insertions, 9 deletions
diff --git a/arch/arm/mach-tegra/headsmp-t2.S b/arch/arm/mach-tegra/headsmp-t2.S index 35d7bf6bf15e..a5a4fb892a1d 100644 --- a/arch/arm/mach-tegra/headsmp-t2.S +++ b/arch/arm/mach-tegra/headsmp-t2.S @@ -136,6 +136,7 @@ ENDPROC(__restart_pllx) ENTRY(tegra_hotplug_startup) setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 bl __invalidate_cpu_state + enable_coresite r1 /* most of the below is a retread of what happens in __v7_setup and * secondary_startup, to get the MMU re-enabled and to branch diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index f3352a731969..d2b8bf8c02d6 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -50,6 +50,7 @@ ENTRY(tegra_secondary_startup) msr cpsr_fsxc, #0xd3 bl __invalidate_cpu_state cpu_id r0 + enable_coresite r1 poke_ev r0, r1 b secondary_startup ENDPROC(tegra_secondary_startup) @@ -57,8 +58,8 @@ ENDPROC(tegra_secondary_startup) /* * __enable_coresite_access * - * Takes the coresite debug interface out of reset, enables - * access to all CPUs. Called with MMU disabled. + * Called only on CPU0 to take the CoreSight debug interface out of + * reset. Called with MMU disabled. */ .align L1_CACHE_SHIFT ENTRY(__enable_coresite_access) @@ -72,14 +73,9 @@ ENTRY(__enable_coresite_access) wait_for_us r3, r2, r4 add r3, r3, #2 bic r1, r1, #(1<<9) - mov32 r5, 0xC5ACCE55 - mov32 r6, (TEGRA_CSITE_BASE + 0x10fb0) @ CPUDBG0_LAR - mov r7, #CONFIG_NR_CPUS wait_until r3, r2, r4 str r1, [r0] -access: str r5, [r6] - add r6, r6, #0x2000 - subs r7, r7, #1 - bhi access + /* Enable CoreSight */ + enable_coresite r3 bx lr ENDPROC(__enable_coresite_access) diff --git a/arch/arm/mach-tegra/power-macros.S b/arch/arm/mach-tegra/power-macros.S index 386bec1737e5..db386df66083 100644 --- a/arch/arm/mach-tegra/power-macros.S +++ b/arch/arm/mach-tegra/power-macros.S @@ -49,3 +49,9 @@ dmb bne 1002b .endm + +/* Enable Coresight access on cpu */ +.macro enable_coresite, tmp + mov32 \tmp, 0xC5ACCE55 + mcr p14, 0, \tmp, c7, c12, 6 +.endm |