diff options
| author | Victor Ryabukhin <vryabukhin@nvidia.com> | 2010-07-30 11:34:54 +0900 |
|---|---|---|
| committer | Janne Hellsten <jhellsten@nvidia.com> | 2010-07-30 01:50:22 -0700 |
| commit | 1d33510105c03d9b041800fc662bef8eaeb7860c (patch) | |
| tree | a50320dd79533bd49b934a168a2108de4cee3883 | |
| parent | 960ba08a655d992addb3d20f40cdfdd8655e7c8b (diff) | |
[NvRm] Fixed calculation of Blinker Timer value
Fix for bug 710667
Previous calculation gave x4 times longer time interval then necessary.
Also algorithm did not work correctly on odd time intervals.
Change-Id: I0f123b27e8102f3f1e49e0ebf507c6a75a3abec0
Reviewed-on: http://git-master/r/4576
Tested-by: Victor Ryabukhin <vryabukhin@nvidia.com>
Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
| -rwxr-xr-x[-rw-r--r--] | arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm.c | 33 | ||||
| -rwxr-xr-x[-rw-r--r--] | arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm_private.h | 5 |
2 files changed, 18 insertions, 20 deletions
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm.c b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm.c index d948fa6f2b18..6cc4e4007c07 100644..100755 --- a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm.c +++ b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm.c @@ -361,7 +361,7 @@ NvError NvRmPwmConfig( NvError status = NvSuccess; NvU32 RegValue = 0, ResultFreqKHz = 0; NvU8 PwmMode = 0; - NvU32 ClockFreqKHz = 0, DCycle = 0, DataOn = 0, DataOff = 0; + NvU32 ClockFreqKHz = 0, DCycle = 0; NvU32 PmcCtrlReg = 0, PmcDpdPadsReg = 0, PmcBlinkTimerReg = 0; NvU32 RequestPeriod = 0, ResultPeriod = 0; NvU32 DataOnRegVal = 0, DataOffRegVal = 0; @@ -500,25 +500,22 @@ NvError NvRmPwmConfig( } else { - RequestPeriod = RequestedFreqHzOrPeriod; + ResultPeriod = RequestedFreqHzOrPeriod; + if (ResultPeriod > MAX_SUPPORTED_PERIOD) + ResultPeriod = MAX_SUPPORTED_PERIOD; + RequestPeriod = ResultPeriod * DATA_FACTOR; + DCycle = DutyCycle>>16; - DataOn = (RequestPeriod * DCycle)/100; - if (DataOn > MAX_SUPPORTED_PERIOD) - { - ResultPeriod = (MAX_SUPPORTED_PERIOD * 100)/DCycle; - DataOn = MAX_SUPPORTED_PERIOD; - } - else - { - ResultPeriod = RequestPeriod; - } - DataOff = ResultPeriod - DataOn; - DataOnRegVal = DataOn * DATA_ON_FACTOR; - if (DataOnRegVal >= MAX_DATA_ON) + if(DCycle > 100) + DCycle = 100; + + DataOnRegVal = (RequestPeriod * DCycle)/100; + if(DataOnRegVal > MAX_DATA_ON) DataOnRegVal = MAX_DATA_ON; - DataOffRegVal = DataOff * DATA_ON_FACTOR; - if (DataOffRegVal >= MAX_DATA_ON) - DataOffRegVal = MAX_DATA_ON; + + DataOffRegVal = RequestPeriod - DataOnRegVal; + if(DataOffRegVal > MAX_DATA_OFF) + DataOffRegVal = MAX_DATA_OFF; PmcCtrlReg = PMC_REGR(hPwm->VirtualAddress[OutputId-1], APBDEV_PMC_CNTRL_0); diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm_private.h b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm_private.h index 46ce0f3a2c3d..4a44864c5a40 100644..100755 --- a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm_private.h +++ b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm_private.h @@ -46,8 +46,9 @@ #define PWM_BANK_SIZE 16 #define PMC_BANK_SIZE 192 #define MAX_SUPPORTED_PERIOD 16 -#define MAX_DATA_ON 0xFFFF -#define DATA_ON_FACTOR 8194 // 8194 = 1/(4 * 30.51us) +#define MAX_DATA_ON 0x7FFF +#define MAX_DATA_OFF 0xFFFF +#define DATA_FACTOR 2048 // 1s / (16 * 30.51us) typedef struct NvRmPwmRec { |